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16th IEEE International Symposium on Applied Computational Intelligence and Informatics, SACI 2022

作者： Ardelean, Sebastian Mihai Udrescu, Mihai Politehnica University of Timisoara Advanced Computing Systems and Architectures Laboratory Department of Computer and Information Technology Timisoara300223 Romania

ISBN: (数字)9781665481250

ISBN: (纸本)9781665481250

Genetic Algorithm (GA) are common probabilistic optimization methods inspired by the process of natural selection. Quantum computers promise substantial speedups over conventional machines, and libraries allow the emulation of circuits on a quantum computer in different highly configurable noise models and even run on quantum computers. Therefore, we need to analyze this class of heuristic methods in the quantum context. We propose a circuit level implementation of the Reduced Quantum Genetic Algorithm (RQGA) using Python and Qiskit. Our main goal is to analyze the circuit complexity from the perspectives of the number of qubits required and the number of quantum gates used. To achieve our goal, we instantiate the framework for solving the knapsack problem, examine the results in a simulated environment, and analyze the circuit's complexity. © 2022 IEEE.

关键词： Heuristic methods

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Evaluating the Knowledge in Test Engineering Education using a Solar-powered Remote-controlled Flying Probe-Inspired In-Circuit Tester

Evaluating the Knowledge in Test Engineering Education using...

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International Symposium for Design and Technology of Electronics Packages (SIITME)

作者： Sorin Liviu Jurj Raul Rotar Ioana Brîncovan Flavius Oprițoiu Mircea Vlăduțiu Computers and Information Technology Department Advanced Computing Systems and Architectures (ACSA) Laboratory “Politehnica” University of Timisoara Timisoara Romania Department of Automation and Applied Informatics Aurel Vlaicu University Arad Romania

ISBN: (数字)9798331539511

ISBN: (纸本)9798331539528

This paper presents a solar-powered remote-controlled Flying Probe-Inspired In-Circuit Tester (FPICT) designed to improve individuals’ knowledge and practical skills in the Test Engineering Education (TEE) domain. The proposed system consists of a user-friendly modern website that offers three main functions: (a) access to TEE-related documentation and tests, (b) a real-time webcam feed for remote monitoring, access, control, and execution of real-time tests on multiple Printed Circuit Boards (PCBs) using the FPICT platform, and (c) performance assessment of users’ TEE knowledge improvement. The effectiveness of the FPICT in enhancing TEE knowledge is evaluated by comparing the score distribution of users before and after the initial tests. Additionally, the power consumption of the FPICT platform is measured, and the feasibility of powering the system with solar energy is investigated. Experimental results demonstrate that the remote-controlled FPICT successfully increases the TEE-related knowledge of web users by an average of $26 \%$ over an average duration of 50 minutes, highlighting its efficacy in teaching theoretical concepts of In-Circuit Testing (ICT) and developing practical skills in the Flying Probe Testing (FPT) domain.

关键词： Knowledge engineering Power measurement Webcams Printed circuits Solar energy Real-time systems Probes Engineering education Remote monitoring Testing

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Systolic Array Architecture for Educational Use

Systolic Array Architecture for Educational Use

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International Conference on System Theory, Control, and computing (ICSTCC)

作者： Flavius Opriţoiu Mircea Vlăduţiu Computer Science and Engineering Department Advanced Computing Systems and Architectures (ACSA) Laboratory Politehnica University Timisoara 2 V.Parvan Blvd Timisoara Romania

This paper presents a systolic array architecture for General Matrix Multiplication. The system was designed and verified using the Verilog description language. The architecture was constructed for educational use aiming to complement the practical activities of Computer Architecture classes. The proposed solution can be used as a design space exploration tool for evaluation of matrix multiplication accelerators based on non-stationary systolic arrays. Both the width and format of the processed operands as well as the number of stages of the systolic array’s Processing Elements can be customized. As a case study, the design and performance of a systolic array for accelerating the multiplication of square matrices of signed, 8-bit integers, is presented. The overall architecture was synthesized for the Altera DE2 FPGA board in order to evaluate its performance.

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Optimal Allocation of STATCOM to Enhance Transient Stability Using Imperialist Competitive Algorithm

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Intelligent Automation & Soft computing 2023年第6期36卷 3425-3446页

作者： Ayman Amer Firas MMakahleh Jafar Ababneh Hani Attar Ahmed Amin Ahmed Solyman Mehrdad Ahmadi Kamarposhti Phatiphat Thounthong Department of Energy Zarqa UniversityZarqa13133Jordan Department of Mechanical Engineering Al-Zaytoonah University of JordanAmman11733Jordan Abdul Aziz Al Ghurair School of Advanced Computing(ASAC) Luminus Technical University CollegeJordan Department of Electrical and Electronics Engineering Faculty of Engineering and ArchitecturesNisantasi UniversityIstanbulTurkey Department of Electrical Engineering Jouybar BranchIslamic Azad UniversityJouybarIran Renewable Energy Research Centre(RERC) Department of Teacher Training in Electrical EngineeringFaculty of Technical EducationKing Mongkut’s University of Technology North Bangkok1518Pracharat 1 RoadBangsueBangkok10800Thailand

With the daily expansion of global energy consumption,developing the power grids is of uttermost ***,building a new trans-mission line is costly and time-consuming,so utilizing the same lines with possible higher transmission capacity is very *** this regard,to increase the capacity of the transmission lines,the flexible alternating current transmission system(FACTS)has been widely used in power grids in recent years by industrialized *** of the essential topics in electrical power systems is the reactive power compensation,and the FACTS plays a significant role in controlling the reactive power current in the power grid and the system voltage oscillations and *** a static synchronous compensator(STATCOM)is embedded in a power system to increase the bus voltage,a supplementary damping controller can be designed to enhance the system oscillation *** the expansion of the grids in the power system,the complexity of their optimization and the extraordinary ability of the imperialist competitive algorithm(ICA)for solving such problems,in this paper,the ICA has been used to determine the optimal position and size of the FACTS devices.

关键词： STATCOM FACTS optimization transient stability imperialist competitive algorithm

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Modeling Chiplet-to-Chiplet (C2C) Communication for Chiplet-based Co-Design

Modeling Chiplet-to-Chiplet (C2C) Communication for Chiplet-...

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ISC High Performance 2025 Research Paper Proceedings (40th International Conference)

作者： Fabian Schätzle Carlos Falquez Nam Ho André Zambanini Johannes van den Boom Estela Suarez Peter Grünberg Institute - Integrated Computing Architectures (ICA — PGI-4) Forschungszentrum Jülich GmbH Jülich Germany Jülich Supercomputing Centre Institute for Advanced Simulation Forschungszentrum Jülich GmbH Jülich Germany SiPEARL Maisons-Laffitte France Computer Science Department University of Bonn Bonn Germany

ISBN: (数字)9783982633619

Chiplet-based processor design, which combines small dies called chiplets to form a larger chip, enables scalable designs at economical costs. This trend has received high attention such that standards for chiplet design have rapidly established, including packaging, protocols, and Chiplet-to-Chiplet (C2C) interfaces. With numerous well-defined chiplet options available, hardware architects would leverage on the co-design process to make optimal decisions on design parameters. An important performance limitation in multi-chiplet designs come from the protocol translation in the C2C communication, needed to maintain cache coherency and avoid risk of deadlocks. When integrating multiple chiplets, deadlocks can happen from both protocol and routing, making deadlock-free designs important. This paper tackles these challenges by introducing a Chiplet-to-Chiplet Gateway (C2CG) architecture, a C2C interface that bridges two chiplet protocols and ensures deadlock-free C2C communication. We also extend the Coherent Hub Interface (CHI) protocol to support cache coherent data sharing among cores across chiplets. The complete design is implemented in the gem5 simulator, constructing a modeling tool for chiplet-based co-design targeting next-generation High-performance computing (HPC) processors. We demonstrate the benefit of the model through a design space exploration of three 64-core Armv8 HPC processor configurations: monolithic, two- and four-chiplet. The exploration, using representative HPC benchmarks, provides insights into C2C parameters and studies the impact of Non-Uniform Memory Access (NUMA) configuration, giving valuable co-design feedback for hardware architects.

关键词： Protocols Translation Chiplets High performance computing Computational modeling Computer architecture System recovery Packaging Hardware Topology

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Affordable Flying Probe-Inspired In-Circuit-Tester for Printed Circuit Boards Evaluation with Application in Test Engineering Education

Affordable Flying Probe-Inspired In-Circuit-Tester for Print...

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International Conference on Environment and Electrical Engineering (EEEIC)

作者： Sorin Liviu Jurj Raul Rotar Flavius Opritoiu Mircea Vladutiu Advanced Computing Systems and Architectures (ACSA) Laboratory “Politehnica” University of Timisoara Timisoara Romania

ISBN: (数字)9781728174556

ISBN: (纸本)9781728174563

This paper presents a hybrid sensorless In-Circuit Tester (ICT) design by combining the features of Flying Probe Testing (FPT) and the capabilities of a Coordinate Measuring Machine (CMM). The experimental results show that the proposed Flying Probe-inspired ICT (FPICT) is suitable for smaller sized Printed Circuit Boards (PCBs) and proves efficient regarding precision (overall precision of 95.70% for the measurements testing), test time (an average of 10.35s for a single-point test cycle), power consumption (an overall of 3.92 Watts for all considered test cases) and cost (around 25 dollars) points of view, being much more affordable and user-friendly when compared to traditional and expensive FPTs found in the industry.

关键词： Testing Probes DC motors Pins Microcontrollers Hardware

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Online Built-In Self-Test Architecture for Automated Testing of a Solar Tracking Equipment

Online Built-In Self-Test Architecture for Automated Testing...

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International Conference on Environment and Electrical Engineering (EEEIC)

作者： Sorin Liviu Jurj Raul Rotar Flavius Opritoiu Mircea Vladutiu Advanced Computing Systems and Architectures (ACSA) Laboratory “Politehnica” University of Timisoara Timisoara Romania

ISBN: (数字)9781728174556

ISBN: (纸本)9781728174563

This paper presents an Online Built-In Self-Test (OBIST) architecture which is tailored towards the detection of hardware faults found in solar tracking systems. The goal of the proposed OBIST is two-folded: first, we identify the idle states of the electrical equipment that orients the payload of a dual-axis solar tracker to the maximum sun exposure with the support of an idle state detector which requires minimum hardware overhead; secondly, when the solar tracking device is in idle state, we disconnect its Circuits Under Test (CUTs) consisting of one Optocoupler, one Arduino UNO and two L298N motor drivers from the main data flow stream (initially connected directly to the solar panel) and attach the proposed OBIST equipment via dedicated switches in order to inject test vectors and collect their output signals in a signature-based response manner. The experimental results based on our hardware implementation and software simulation achieve an average of 93.93% coverage for single bit-flip errors (last 8 bits, mutant), 100% coverage for single stuck-at-faults (8, 12 and 16 random bits) as well as 96.96% for all targeted faults, showing that the proposed OBIST architecture is efficient with regard to test coverage and cost points of view.

关键词： Circuit faults Built-in self-test Hardware Computer architecture Integrated circuits Sun

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QC pp >: AAA behavioral quantum computing simulation library 12

QC pp >: AAA behavioral quantum computing simulation library

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12th IEEE International Symposium on Applied Computational Intelligence and Informatics, SACI 2018

作者： Ardelean, Sebastian Mihai Udrcscu, Mihai Computer Engineering Department University 'Po-litehnica' of Timisoara Advanced Computing Systems and Architectures Laboratory 2V. Parvan Boulevard Timisoara300223 Romania

ISBN: (纸本)9781538646403

In this paper we describe a quantum computing simulation library named QC \vert pp\rangle. In the state-of-the-art most of the available libraries and simulators make use of the structural modeling of quantum circuits which requires a high memory consumption and huge runtime. Indeed, under the structural modeling framework, the simulation of quantum computers for n qubits entails multiplication of sparse 2{n}\times 2{n} size matrices with vectors of dimension 2{n}, thus making this a memory-bound application. Through QC \vert pp\rangle we propose a behavioral modeling framework of quantum circuits to reduce memory consumption, increase performance and allow for testing our simulator on more qubits. We will also present the results obtained by testing our library on simulating Grover's algorithm. © 2018 IEEE.

关键词： Qubits

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Quantum singular value transformation and beyond: Exponential improvements for quantum matrix arithmetics

arXiv

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arXiv 2018年

作者： Gilyén, András Su, Yuan Low, Guang Hao Wiebe, Nathan QuSoft Cwi University of Amsterdam Netherlands Department of Computer Science Institute for Advanced Computer Studies Joint Center for Quantum Information and Computer Science University of Maryland United States Microsoft Research Quantum Architectures and Computing Group United States

Quantum computing is powerful because unitary operators describing the time-evolution of a quantum system have exponential size in terms of the number of qubits present in the system. We develop a new "Singular value transformation" algorithm capable of harnessing this exponential advantage, that can apply polynomial transformations to the singular values of a block of a unitary, generalizing the optimal Hamiltonian simulation results of Low and Chuang [LC17a]. The proposed quantum circuits have a very simple structure, often give rise to optimal algorithms and have appealing constant factors, while typically only use a constant number of ancilla qubits. We show that singular value transformation leads to novel algorithms. We give an efficient solution to a "non-commutative" measurement problem used for efficient ground-state-preparation of certain local Hamiltonians, and propose a new method for singular value estimation. We also show how to exponentially improve the complexity of implementing fractional queries to unitaries with a gapped spectrum. Finally, as a quantum machine learning application we show how to efficiently implement principal component regression. "Singular value transformation" is conceptually simple and efficient, and leads to a unified framework of quantum algorithms incorporating a variety of quantum speed-ups. We illustrate this by showing how it generalizes a number of prominent quantum algorithms, and quickly derive the following algorithms: Optimal Hamiltonian simulation, implementing the Moore-Penrose pseudoinverse with exponential precision, fixed-point amplitude amplification, robust oblivious amplitude amplification, fast QMA amplification, fast quantum OR lemma, certain quantum walk results and several quantum machine learning algorithms. In order to exploit the strengths of the presented method it is useful to know its limitations too, therefore we also prove a lower bound on the efficiency of singular value transformation, which of

关键词： Hamiltonians

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Bayesian inference for randomized benchmarking protocols

arXiv

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arXiv 2018年

作者： Hincks, Ian Wallman, Joel J. Ferrie, Chris Granade, Chris Cory, David G. Department of Applied Mathematics University of Waterloo WaterlooON Canada Institute for Quantum Computing University of Waterloo WaterlooON Canada Centre for Quantum Software and Information University of Technology Sydney UltimoNSW2007 Australia Quantum Architectures and Computation Microsoft Research RedmondWA98052 United States Department of Chemistry University of Waterloo WaterlooON Canada Perimeter Institute for Theoretical Physics WaterlooON Canada Canadian Institute for Advanced Research TorontoON Canada

Randomized benchmarking (RB) protocols are standard tools for characterizing quantum devices. Prior analyses of RB protocols have not provided a complete method for analyzing realistic data, resulting in a variety of ad-hoc methods. The main confounding factor in rigorously analyzing data from RB protocols is an unknown and noise-dependent distribution of survival probabilities over random sequences. We propose a hierarchical Bayesian method where these survival distributions are modeled as nonparametric Dirichlet process mixtures. Our method infers parameters of interest without additional assumptions about the underlying physical noise process. We show with numerical examples that our method works robustly for both standard and highly pathological error models. Our method also works reliably at low noise levels and with little data because we avoid the asymptotic assumptions of commonly used methods such as least-squares fitting. For example, our method produces a narrow and consistent posterior for the average gate fidelity from ten random sequences per sequence length in the standard RB protocol. Copyright © 2018, The Authors. All rights reserved.

关键词： Benchmarking

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