The Rapid Prototyping of Application Specific Signal Processors (RASSP) program is a multi-year DARPA/Tri-Service initiative intended to dramatically improve the process by which complex digital systems, particularly ...
The Rapid Prototyping of Application Specific Signal Processors (RASSP) program is a multi-year DARPA/Tri-Service initiative intended to dramatically improve the process by which complex digital systems, particularly embedded digital signal processors, are designed, manufactured, upgraded, and supported. This paper reviews the genesis of the RASSP program, considering both the problems that defined the need for the program, and the historical conditions under which it began. The RASSP program is then presented from two viewpoints. The first is programmatic, covering the goals and constraints of the program, and describing the roles of the various program participants. The second is technical, covering the major concepts upon which the developing RASSP approach to design is based and showing how the detailed technical discussions contained in the other papers in this issue of the Journal of VLSI Signal Processing relate to one another and fit into an overall development concept. The paper closes with a review of the status of the program as of this writing (Summer 1996).
In an approach proposed by V.P. Kumar et al. (see Proc. IEEE Int. Conf. on Computer-Aided Design, p.226-9, Nov. 1989) for the yield enhancement of programmable gate arrays (PGAs), an initial placement of a circuit is ...
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In an approach proposed by V.P. Kumar et al. (see Proc. IEEE Int. Conf. on Computer-Aided Design, p.226-9, Nov. 1989) for the yield enhancement of programmable gate arrays (PGAs), an initial placement of a circuit is first obtained using a standard technique such as simulated annealing on a defect-free PGA. In the next step this placement is reconfigured so that the circuit is mapped onto the defect-free portion of a defective PGA chip with the same architecture. In the present work, the authors consider the problem of yield enhancement along the same lines as above not only for PGAs but also for wafer-scale-integrated arrays. A heuristic algorithm for reconfiguration based on a graph-theoretic formulation of the problem and a polynomial-time exact algorithm for a special case of the problem are presented. The reconfiguration algorithms are evaluated by comparing the routability and wire length of the reconfigured and initial placements of the circuit.< >
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