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Circuit level implementation of the Reduced Quantum Genetic Algorithm using Qiskit 16

Circuit level implementation of the Reduced Quantum Genetic ...

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16th IEEE International Symposium on Applied Computational Intelligence and Informatics, SACI 2022

作者： Ardelean, Sebastian Mihai Udrescu, Mihai Politehnica University of Timisoara Advanced Computing Systems and Architectures Laboratory Department of Computer and Information Technology Timisoara300223 Romania

ISBN: (数字)9781665481250

ISBN: (纸本)9781665481250

Genetic Algorithm (GA) are common probabilistic optimization methods inspired by the process of natural selection. Quantum computers promise substantial speedups over conventional machines, and libraries allow the emulation of circuits on a quantum computer in different highly configurable noise models and even run on quantum computers. Therefore, we need to analyze this class of heuristic methods in the quantum context. We propose a circuit level implementation of the Reduced Quantum Genetic Algorithm (RQGA) using Python and Qiskit. Our main goal is to analyze the circuit complexity from the perspectives of the number of qubits required and the number of quantum gates used. To achieve our goal, we instantiate the framework for solving the knapsack problem, examine the results in a simulated environment, and analyze the circuit's complexity. © 2022 IEEE.

关键词： Heuristic methods

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Evaluating the Knowledge in Test Engineering Education using a Solar-powered Remote-controlled Flying Probe-Inspired In-Circuit Tester

Evaluating the Knowledge in Test Engineering Education using...

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International Symposium for Design and Technology of Electronics Packages (SIITME)

作者： Sorin Liviu Jurj Raul Rotar Ioana Brîncovan Flavius Oprițoiu Mircea Vlăduțiu Computers and Information Technology Department Advanced Computing Systems and Architectures (ACSA) Laboratory “Politehnica” University of Timisoara Timisoara Romania Department of Automation and Applied Informatics Aurel Vlaicu University Arad Romania

ISBN: (数字)9798331539511

ISBN: (纸本)9798331539528

This paper presents a solar-powered remote-controlled Flying Probe-Inspired In-Circuit Tester (FPICT) designed to improve individuals’ knowledge and practical skills in the Test Engineering Education (TEE) domain. The proposed system consists of a user-friendly modern website that offers three main functions: (a) access to TEE-related documentation and tests, (b) a real-time webcam feed for remote monitoring, access, control, and execution of real-time tests on multiple Printed Circuit Boards (PCBs) using the FPICT platform, and (c) performance assessment of users’ TEE knowledge improvement. The effectiveness of the FPICT in enhancing TEE knowledge is evaluated by comparing the score distribution of users before and after the initial tests. Additionally, the power consumption of the FPICT platform is measured, and the feasibility of powering the system with solar energy is investigated. Experimental results demonstrate that the remote-controlled FPICT successfully increases the TEE-related knowledge of web users by an average of $26 \%$ over an average duration of 50 minutes, highlighting its efficacy in teaching theoretical concepts of In-Circuit Testing (ICT) and developing practical skills in the Flying Probe Testing (FPT) domain.

关键词： Knowledge engineering Power measurement Webcams Printed circuits Solar energy Real-time systems Probes Engineering education Remote monitoring Testing

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Systolic Array Architecture for Educational Use

Systolic Array Architecture for Educational Use

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International Conference on System Theory, Control, and computing (ICSTCC)

作者： Flavius Opriţoiu Mircea Vlăduţiu Computer Science and Engineering Department Advanced Computing Systems and Architectures (ACSA) Laboratory Politehnica University Timisoara 2 V.Parvan Blvd Timisoara Romania

This paper presents a systolic array architecture for General Matrix Multiplication. The system was designed and verified using the Verilog description language. The architecture was constructed for educational use aiming to complement the practical activities of Computer Architecture classes. The proposed solution can be used as a design space exploration tool for evaluation of matrix multiplication accelerators based on non-stationary systolic arrays. Both the width and format of the processed operands as well as the number of stages of the systolic array’s Processing Elements can be customized. As a case study, the design and performance of a systolic array for accelerating the multiplication of square matrices of signed, 8-bit integers, is presented. The overall architecture was synthesized for the Altera DE2 FPGA board in order to evaluate its performance.

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Affordable Flying Probe-Inspired In-Circuit-Tester for Printed Circuit Boards Evaluation with Application in Test Engineering Education

Affordable Flying Probe-Inspired In-Circuit-Tester for Print...

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International Conference on Environment and Electrical Engineering (EEEIC)

作者： Sorin Liviu Jurj Raul Rotar Flavius Opritoiu Mircea Vladutiu Advanced Computing Systems and Architectures (ACSA) Laboratory “Politehnica” University of Timisoara Timisoara Romania

ISBN: (数字)9781728174556

ISBN: (纸本)9781728174563

This paper presents a hybrid sensorless In-Circuit Tester (ICT) design by combining the features of Flying Probe Testing (FPT) and the capabilities of a Coordinate Measuring Machine (CMM). The experimental results show that the proposed Flying Probe-inspired ICT (FPICT) is suitable for smaller sized Printed Circuit Boards (PCBs) and proves efficient regarding precision (overall precision of 95.70% for the measurements testing), test time (an average of 10.35s for a single-point test cycle), power consumption (an overall of 3.92 Watts for all considered test cases) and cost (around 25 dollars) points of view, being much more affordable and user-friendly when compared to traditional and expensive FPTs found in the industry.

关键词： Testing Probes DC motors Pins Microcontrollers Hardware

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Online Built-In Self-Test Architecture for Automated Testing of a Solar Tracking Equipment

Online Built-In Self-Test Architecture for Automated Testing...

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International Conference on Environment and Electrical Engineering (EEEIC)

作者： Sorin Liviu Jurj Raul Rotar Flavius Opritoiu Mircea Vladutiu Advanced Computing Systems and Architectures (ACSA) Laboratory “Politehnica” University of Timisoara Timisoara Romania

ISBN: (数字)9781728174556

ISBN: (纸本)9781728174563

This paper presents an Online Built-In Self-Test (OBIST) architecture which is tailored towards the detection of hardware faults found in solar tracking systems. The goal of the proposed OBIST is two-folded: first, we identify the idle states of the electrical equipment that orients the payload of a dual-axis solar tracker to the maximum sun exposure with the support of an idle state detector which requires minimum hardware overhead; secondly, when the solar tracking device is in idle state, we disconnect its Circuits Under Test (CUTs) consisting of one Optocoupler, one Arduino UNO and two L298N motor drivers from the main data flow stream (initially connected directly to the solar panel) and attach the proposed OBIST equipment via dedicated switches in order to inject test vectors and collect their output signals in a signature-based response manner. The experimental results based on our hardware implementation and software simulation achieve an average of 93.93% coverage for single bit-flip errors (last 8 bits, mutant), 100% coverage for single stuck-at-faults (8, 12 and 16 random bits) as well as 96.96% for all targeted faults, showing that the proposed OBIST architecture is efficient with regard to test coverage and cost points of view.

关键词： Circuit faults Built-in self-test Hardware Computer architecture Integrated circuits Sun

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QC pp >: AAA behavioral quantum computing simulation library 12

QC pp >: AAA behavioral quantum computing simulation library

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12th IEEE International Symposium on Applied Computational Intelligence and Informatics, SACI 2018

作者： Ardelean, Sebastian Mihai Udrcscu, Mihai Computer Engineering Department University 'Po-litehnica' of Timisoara Advanced Computing Systems and Architectures Laboratory 2V. Parvan Boulevard Timisoara300223 Romania

ISBN: (纸本)9781538646403

In this paper we describe a quantum computing simulation library named QC \vert pp\rangle. In the state-of-the-art most of the available libraries and simulators make use of the structural modeling of quantum circuits which requires a high memory consumption and huge runtime. Indeed, under the structural modeling framework, the simulation of quantum computers for n qubits entails multiplication of sparse 2{n}\times 2{n} size matrices with vectors of dimension 2{n}, thus making this a memory-bound application. Through QC \vert pp\rangle we propose a behavioral modeling framework of quantum circuits to reduce memory consumption, increase performance and allow for testing our simulator on more qubits. We will also present the results obtained by testing our library on simulating Grover's algorithm. © 2018 IEEE.

关键词： Qubits

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Simulated Fault Injection for Quantum Circuits Based on Simulator Commands

Simulated Fault Injection for Quantum Circuits Based on Simu...

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International Symposium on Applied Computational Intelligence and Informatics ( SACI)

作者： Oana Boncalo Mihai Udrescu Lucian Prodan Mircea Vladutiu Alexandru Amaricai Advanced Computing Systems and Architectures Laboratory-Department of Computer Science and Engineering University of Politehnica Timisoara Romania

This paper addresses the problem of evaluating the fault tolerance algorithms and methodologies (FTAMS) designed for quantum circuits, by making use of fault injection techniques. These techniques are inspired from their rich classical counterparts, and were adapted to the quantum computation specific features, including the available error models. Because of their wide spectrum of application, including quantum circuit simulation, and their flexibility in circuit representation (i.e. both behavioral and structural descriptions of a circuit are possible), the hardware description languages (HDLs) appear as the best choice for our simulation experiments. The techniques employed for fault injection are based on simulator commands. The simulation results for the fault-affected circuit were compared to the outputs of a Gold circuit (a faultless circuit) in order to compute the quantum failure rate.

关键词： Circuit simulation Circuit faults Computational modeling Quantum computing Flexible printed circuits Fault tolerance Design methodology Algorithm design and analysis Hardware design languages Gold

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Assessing quantum circuits reliability with mutant-based simulated fault injection

Assessing quantum circuits reliability with mutant-based sim...

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European Conference on Circuit Theory and Design, ECCTD

作者： Oana Boncalo Mihai Udrescu Lucian Prodan Mircea Vladutiu Alexandru Amaricai Advanced Computing Systems and Architectures Laboratory - Department of Computer Science and Engineering University of Politehnica Timisoara Romania

This paper addresses the problem of evaluating the fault tolerance algorithms and methodologies (FTAMs) for quantum circuits, by making use of fault injection techniques. The proposed mutant-based fault injection techniques are inspired from their classical counterparts [T.A. DeLong et al., 1996] [E. Jenn et al., 1994], and were adapted to the specific features of quantum computation, including the available error models [J. P. Hayes et al., 2004] [E. Knill et al., 1997]. The HDLs were employed in order to perform fault injection, due to their capacity of behavioral and structural circuit description, as well as their hierarchical features. Besides providing a much realistic description, the experimental simulated fault injection campaigns provide quantitative means for quantum fault tolerance assessment.

关键词： Circuit simulation Circuit faults Quantum computing Computational modeling Fault tolerance Hilbert space Quantum entanglement Computer architecture Hardware design languages Vectors

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Implementing quantum genetic algorithms: A solution based on Grover's algorithm

Implementing quantum genetic algorithms: A solution based on...

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3rd Conference on computing Frontiers 2006, CF '06

作者： Udrescu, Mihai Prodan, Lucian VlǍduţiu, Mircea Advanced Computing Systems and Architectures Laboratory Computer Engineering Department University Politehnica of Timişoara 2 V. Parvan Boulevard Timişoara 300223 Romania

ISBN: (纸本)1595933026

This paper presents a new methodology for running Genetic Algorithms on a Quantum Computer. To the best of our knowledge and according to reference [6] there are no feasible solutions for the implementation of the Quantum Genetic Algorithms (QGAs). We present a new perspective on how to build the corresponding QGA architecture. It turns out that the genetic strategy is not particularly helpful in our quantum computation approach;therefore our solution consists of designing a special-purpose oracle that will work with a modified version of an already known algorithm (maximum finding [1]), in order to reduce the QGAs to a Grover search. Quantum computation offers incentives for this approach, due to the fact that the qubit representation of the chromosome can encode the entire population as a superposition of basis-state values. Copyright 2006 ACM.

关键词： Genetic algorithms

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Multiple-level concatenated coding in embryonics: A dependability analysis 05

Multiple-level concatenated coding in embryonics: A dependab...

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GECCO 2005 - Genetic and Evolutionary Computation Conference

作者： Prodan, Lucian Udrescu, Mihai Vladutiu, Mircea Advanced Computing Systems and Architectures Laboratory Politehnica University Computer Department 2 V.Parvan Blvd. 300223 Timisoara TM Romania

ISBN: (纸本)1595930108

computing machines require the highest possible dependability in order to provide accurate functionality in aggressive, critical environments. For this purpose, the Embryonics (for embryonic electronics) project explores Nature's structural redundancy mechanisms in digital electronics. It offers a hierarchically reconfigurable framework [4][5][18], whose effectiveness was assessed only for some particular cases [8]. Following the introduction of specialized memory structures [10][13], this paper proposes a more thorough reliability analysis, inspired by faulttolerant quantum computing theory. After adopting the accuracy threshold measure as the main parameter for our qualitative evaluation, the concepts and implementation details about concatenated coding are presented. This technique, also inspired from reliable quantum computing, seems particularly well suited for the multiple-level architecture in Embryonics and allows preserving arbitrary long fault-tolerant computation. Copyright 2005 ACM.

关键词： Encoding (symbols)

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