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Special issue on selected papers from the third annual workshop on algorithms and computation (WALCOM 2009)

Journal of Graph Algorithms and Applications 2011年第3期15卷 319-321页

作者： Das, Sandip Uehara, Ryuhei Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata 700 108 India Asahidai 1-1 Ishikawa 923-1292 Japan

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Resource-aware scheduling of multiple quantum circuits on a hardware device

arXiv

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arXiv 2024年

作者： Bhoumik, Debasmita Majumdar, Ritajit Sur-Kolay, Susmita Advanced Computing & Microelectronics Unit Indian Statistical Institute India IBM Quantum IBM India Research Lab India

Recent quantum technologies and quantum error-correcting codes emphasize the requirement for arranging interacting qubits in a nearest-neighbor (NN) configuration while mapping a quantum circuit onto a given hardware device, in order to avoid undesirable noise. It is equally important to minimize the wastage of qubits in a quantum hardware device with m qubits while running circuits of n qubits in total, with n © 2024, CC BY.

关键词： Timing circuits

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Formal Methods for Ranking Counterexamples Through Assumption Mining 12

Formal Methods for Ranking Counterexamples Through Assumptio...

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Design, Automation & Test in Europe Conference & Exhibition

作者： Srobona Mitra Ansuman Banerjee Pallab Dasgupta Indian Institute of Technology Kharagpur Kharagpur India Advanced Computing & Microelectronics Unit Indian Statistical Institute Kolkata India

ISBN: (纸本)9783981080186

Bug-fixing in deeply embedded portions of the logic is typically accompanied by the post-facto addition to new assertions which cover the bug scenario. Formally verifying properties defined over such deeply embedded portions of the logic is challenging because formal methods do not scale to the size of the entire logic, and verifying the property on the embedded logic in isolation typically throws up a large number of counterexamples, many of which are spurious because the scenarios they depict are not possible in the entire logic. In this paper we introduce the notion of ranking the counterexamples so that only the most likely counterexamples are presented to the designer. Our ranking is based on assume properties mined from simulation traces of the entire logic. We define a metric to compute a belief for each assume property that is mined, and rank counterexamples based on their conflicts with the mined assume properties. Experimental results demonstrate an amazing correlation between the real counterexamples (if they exist) and the proposed ranking metric, thereby establishing the proposed method as a very promising verification approach.

关键词： Formal logic Designers Conflict (Psychology) embedding Beliefs Entire mining Metric Metronidazole

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Efficient Syndrome Decoder for Heavy Hexagonal QECC via Machine Learning

arXiv

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arXiv 2022年

作者： Bhoumik, Debasmita Majumdar, Ritajit Madan, Dhiraj Vinayagamurthy, Dhinakaran Raghunathan, Shesha Sur-Kolay, Susmita Advanced Computing & Microelectronics Unit Indian Statistical Institute India IBM Quantum IBM India Research Lab India

Error syndromes for heavy hexagonal code and other topological codes such as surface code have typically been decoded by using Minimum Weight Perfect Matching (MWPM) based methods. Recent advances have shown that topological codes can be efficiently decoded by deploying machine learning (ML) techniques, in particular with neural networks. In this work, we first propose an ML based decoder for heavy hexagonal code and establish its efficiency in terms of the values of threshold and pseudo-threshold, for various noise models. We show that the proposed ML based decoding method achieves ∼ 5× higher values of threshold than that for MWPM. Next, exploiting the property of subsystem codes, we define gauge equivalence for heavy hexagonal code, by which two distinct errors can belong to the same error class. A linear search based method is proposed for determining the equivalent error classes. This provides a quadratic reduction in the number of error classes to be considered for both bit flip and phase flip errors, and thus a further improvement of ∼ 14% in the threshold over the basic ML decoder. Lastly, a novel technique based on rank to determine the equivalent error classes is presented, which is empirically faster than the one based on linear search. © 2022, CC BY.

关键词： Gages

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A machine learning based heuristic to predict the efficacy of online sale

arXiv

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arXiv 2020年

作者： Singhania, Aditya Vikram Mukherjee, Saronyo Lal Majumdar, Ritajit Mehta, Akash Banerjee, Priyanka Bhoumik, Debasmita Department of Computer Science Bhawanipur Education Society College Advanced Computing & Microelectronics Unit Indian Statistical Institute India

It is difficult to decide upon the efficacy of an online sale simply from the discount offered on commodities. Different features have different influence on the price of a product which must be taken into consideration when determining the significance of a discount. In this paper we have proposed a machine learning based heuristic to quantify the "significance" of the discount offered on any commodity. Our proposed technique can quantify the significance of the discount based on features and the original price, and hence can guide a buyer during a sale season by predicting the efficacy of the sale. We have applied this technique on the Flipkart Summer Sale dataset using Support Vector Machine, which predicts the efficacy of the sale with an accuracy of 91.11%. Our result shows that very few mobile phones have a significant discount during the Flipkart Summer Sale. Copyright © 2020, The Authors. All rights reserved.

关键词： Electronic commerce

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A Generalized Theory for Formal Assertion Coverage

A Generalized Theory for Formal Assertion Coverage

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Asian Test Symposium (ATS)

作者： Sourasis Das Ansuman Banerjee Pallab Dasgupta Department of Computer Science and Engineering IIT Kharagpur India Advanced Computing and Microelectronics Unit Indian Statistical Institute India

Coverage of formal property specifications has important ramifications in design verification. Mutation coverage, a well studied approach towards specification coverage, checks whether the specification fails in the presence of a fault. Existing mutation coverage methods are broadly divided into those which inject the fault into a given implementation and those which inject the fault directly into the specification. This paper presents a theory which unifies these contrasting approaches and extends the mutation coverage approach to partial implementations where some components are given, and for the others, we only have component specifications.

关键词： Topology Cost accounting Standards Protocols Performance evaluation microelectronics Computer bugs

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Length-based anchor-free localization in a fully covered sensor network

Length-based anchor-free localization in a fully covered sen...

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International Communication Systems and Networks and Workshops, COMSNETS

作者： B. Sau K. Mukhopadhyaya Department of Mathematics Jadavpur University Kolkata India Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata India

Localization is an important issue for Wireless Sensor Networks (WSN). We consider a WSN consisting of identical sensors. All known distances between the sensors are assumed to be less than the communication range of the sensors and all unknown distances greater. We also assume that the communication range is at least twice as much as the sensing range. Every point in the field of interest is assumed to be within the sensing zone of some sensor. Under this model, we propose an anchor-free length-based localization algorithm. The worst case time complexity of the algorithm is O(|E|) (where E is the set of edges of the network graph). We carry out simulation studies to observe that under uniform distribution, the number of edges is actually much lower than n 2 , if just about enough sensors are deployed to cover the total field. We prove that, under this model, the solution to the localization problem is unique. We also provide a simple technique for verifying the assumption that all points in the field are covered.

关键词： Wireless sensor networks Hardware Global Positioning System Computer networks microelectronics Mathematics User-generated content Government Routing Information security

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Minimum Dominating Set Problem for unit Disks Revisited

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International Journal of Computational Geometry and Applications 2015年第3期25卷 227-244页

作者： Carmi, Paz Das, Gautam K. Jallu, Ramesh K. Nandy, Subhas C. Prasad, Prajwal R. Stein, Yael Department of Computer Science Ben-Gurion University of the Negev Beer-Sheva 84105 Israel Department of Mathematics Indian Institute of Technology Guwahati Guwahati 781039 India Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata 700108 India National Institute of Technology Karnataka Mangalore 575025 India

In this article, we study approximation algorithms for the problem of computing minimum dominating set for a given set S of n unit disks in R2. We first present a simple O(nlogk) time 5-factor approximation algorithm ... 详细信息

In this article, we study approximation algorithms for the problem of computing minimum dominating set for a given set S of n unit disks in R². We first present a simple O(nlogk) time 5-factor approximation algorithm for this problem, where k is the size of the output. The best known 4-factor and 3-factor approximation algorithms for the same problem run in time O(n8logn) and O(n15logn) respectively [M. De, G. K. Das, P. Carmi and S. C. Nandy, Approximation algorithms for a variant of discrete piercing set problem for unit disks, Int. J. of Computational Geometry and Appl., 22(6):461-477, 2013]. We show that the time complexity of the in-place 4-factor approximation algorithm for this problem can be improved to O(n6logn). A minor modification of this algorithm produces a 143-factor approximation algorithm in O(n5logn) time. The same techniques can be applied to have a 3-factor and a 4513-factor approximation algorithms in time O(n11logn) and O(n10logn) respectively. Finally, we propose a very important shifting lemma, which is of independent interest, and it helps to present 52-factor approximation algorithm for the same problem. It also helps to improve the time complexity of the proposed PTAS for the problem. © 2015 World Scientific Publishing Company.

关键词： approximation algorithm Minimum dominating set unit disk graph

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On the Span of l Distance Coloring of Infinite Hexagonal Grid

arXiv

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arXiv 2022年

作者： Ghosh, Sasthi C. Koley, Subhasis Advanced Computing and Microelectronics Unit Indian Statistical Institute 203 B. T. Road Kolkata700108 India

For a graph G(V, E) and l ∈ , an l distance coloring is a coloring f : V → {1, 2, · · ·, n} of V such that ∀u, v ∈ V, u ≠ v, f(u) ≠ f(v) when d(u, v) ≤ l. Here d(u, v) is the distance between u an... 详细信息

For a graph G(V, E) and l ∈ , an l distance coloring is a coloring f : V → {1, 2, · · ·, n} of V such that ∀u, v ∈ V, u ≠ v, f(u) ≠ f(v) when d(u, v) ≤ l. Here d(u, v) is the distance between u and v and is equal to the minimum number of edges that connect u and v in G. The span of l distance coloring of G, λl(G), is the minimum n among all l distance coloring of G. A class of channel assignment problem in cellular network can be formulated as a distance graph coloring problem in regular grid graphs. The cellular network is often modelled as an infinite hexagonal grid TH, and hence determining λl(TH) has relevance from practical point of view. Jacko and Jendrol [Discussiones Mathematicae Graph Theory, 2005] determined the exact value of λl(TH) for any odd l and for even l ≥ 8, it is conjectured that (Equation presented) where [x] is an integer, x ∈ and (Equation presented). For l = 8, the conjecture has been proved by Sasthi and Subhasis [22nd Italian Conference on Theoretical Computer Science, 2021]. In this paper, we prove the conjecture for any l ≥ 10. © 2022, CC BY.

关键词： Coloring

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A Graph-Based 3D IC Partitioning Technique

A Graph-Based 3D IC Partitioning Technique

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IEEE Computer Society Annual Symposium on VLSI

作者： Sabyasachee Banerjee Subhashis Majumder Bhargab B. Bhattacharya Department of Computer Science and Engineering Heritage Institute of Technology Kolkata Advanced Computing & Microelectronics Unit Indian Statistical Institute Kolkata

Netlist partitioning is an important part of the physical design of 3D IC chips. Each subcircuit corresponding to a partition is subsequently assigned to a suitable device layer in the design phase. This paper proposes a netlist partitioning technique that intends to minimize the number of inter-layer interconnections while maintaining the area constraints. This, in turn, will minimize the area and cost associated with the Through-Silicon Vias (TSVs) needed in the design. The proposed method starts with an BFS-based initial solution and then improves iteratively using a heuristic. Experimental results demonstrate that by reassigning some modules to other layers, our algorithm could achieve up to 45% reduction in the number of TSVs on several benchmark circuits compared to earlier approaches. The resulting increase in floor area due to movement of modules a cross layers, is almost compensated by the decrease in TSV-area. Thus while satisfying the area-constraints, it allows us to reduce the number of TSVs as well as the IR-drop and delay associated with the vias.

关键词： Partitioning algorithms Three-dimensional displays Through-silicon vias Algorithm design and analysis Benchmark testing Time complexity

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