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Asymptotically improved circuit for a d-ary Grover's algorithm with advanced decomposition of the n-qudit Toffoli gate

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Physical Review A 2022年第6期105卷 062453-062453页

作者： Amit Saha Ritajit Majumdar Debasri Saha Amlan Chakrabarti Susmita Sur-Kolay A. K. Choudhury School of Information Technology University of Calcutta Calcutta 700106 India ATOS Pune 411045 India Advanced Computing & Microelectronics Unit Indian Statistical Institute Calcutta 700108 India

The progress in building quantum computers to execute quantum algorithms has recently been remarkable. Grover's search algorithm in a binary quantum system provides a considerable speed-up over the classical paradigm. It can be extended to a d-ary (qudit) quantum system also for utilizing the advantage of larger state space, which helps to reduce the runtime of the algorithm as compared to the traditional binary quantum systems. In a qudit quantum system, an n-qudit Toffoli gate plays a significant role in the accurate implementation of Grover's algorithm. In this article, a generalized n-qudit Toffoli gate is realized using higher-dimensional qudits to attain a logarithmic depth decomposition without ancilla qudit. The circuit for Grover's algorithm has then been designed for any d-ary quantum system, where d≥2, with the proposed n-qudit Toffoli gate to obtain optimized depth compared to earlier approaches. The technique for decomposing an n-qudit Toffoli gate requires access to two immediately higher-energy levels, making the design susceptible to errors. Nevertheless, we show that the percentage decrease in the probability of error is significant with both gate count and circuit depth reduced as compared to that in state-of-the-art works.

关键词： Quantum computation Quantum engineering

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An empirical study of incremental learning in neural network with noisy training set

arXiv

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arXiv 2020年

作者： Chatterjee, Atrayee Ganguly, Shovik Bhoumik, Debasmita Majumdar, Ritajit Asutosh College University of Calcutta Lexmark International India Pvt. Ltd Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata India

The notion of incremental learning is to train an ANN algorithm in stages, as and when newer training data arrives. Incremental learning is becoming widespread in recent times with the advent of deep learning. Noise in the training data reduces the accuracy of the algorithm. In this paper, we make an empirical study of the effect of noise in the training phase. We numerically show that the accuracy of the algorithm is dependent more on the location of the error than the percentage of error. Using Perceptron, Feed Forward Neural Network and Radial Basis Function Neural Network, we show that for the same percentage of error, the accuracy of the algorithm significantly varies with the location of error. Furthermore, our results show that the dependence of the accuracy with the location of error is independent of the algorithm. However, the slope of the degradation curve decreases with more sophisticated algorithms. Copyright © 2020, The Authors. All rights reserved.

关键词： Errors

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A thermal and congestion driven global router for 3D integrated circuits

A thermal and congestion driven global router for 3D integra...

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IEEE Students' Technology Symposium (TechSym)

作者： Debashri Roy Prasun Ghosal Nabanita Das Department of IT Bengal Engineering and Science University Shibpur Howrah WB INDIA Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata WB INDIA

During recent days, the large problem space of very large scale integrated (VLSI) circuits has led global routing problem to a NP Complete one. With the advent of three dimensional integrated circuits (3D IC) the problem has become more complex. In this paper, a multi-objective global routing technique is formulated using fuzzy logic to get rid of the limitations of deterministic approaches. During global routing the decision is taken from a fuzzy logic expert system depending upon some generated pre-routing guiding information. Proposed approach is mainly focused on the modern generation 3D ICs. This primary work is mainly incorporated in the standard cell design for 3D ICs. A two-pin global router tool is designed based on the proposed algorithm resulting 85-97% routability in negligible time for ISPD'98 benchmarks.

关键词： Routing Three-dimensional displays Expert systems Benchmark testing Integrated circuits Sensitivity Fuzzy logic

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Impact of Inductance on the Performance of Single Walled Carbon Nanotube Bundle Interconnects

Impact of Inductance on the Performance of Single Walled Car...

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International Symposium on Electronic System Design (ISED)

作者： Manodipan Sahoo Hafizur Rahaman Bhargab Bhattacharya Department of Information Technology Bengal Engineering & Science University Shibpur Howrah India Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata India

In this work, we have studied the inductive properties of interconnects built with Single Walled Carbon Nan tube (SWCNT) bundle. We have used the most recent ITRS-2011 data while estimating the RLC parameters of SWCNT bundle interconnects. In our analysis, we have used the classical ABCD-parameter-matrix based method and a delay allowance of 50%. Simulations are performed for both sparse and dense SWCNT bundle interconnects at 21 nm and 15 nm technology nodes, considering three levels of their application: local, intermediate, and global. It is observed that for a 100 MHz periodic square wave input with a rise time of 10 ps, SWCNT bundle interconnects are not impacted by inductance. It is shown that for the given input signal and SWCNT bundle parameters, the length over which the inductive effects will be more prominent, has little practical significance. It is quantitatively shown that the inductive effects will mostly impact the long-intermediate and global interconnects. With technology scaling, such effects may worsen the performance. It is also observed that the Elmore-based methodology for delay estimation of SWCNT bundle interconnects predicts the actual delay very accurately with a maximum error of only 5.46%.

关键词： Inductance Delays Integrated circuit interconnections Resistance Quantum capacitance Carbon nanotubes

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Scalable and Fair Resource Sharing Among 5G D2D Users and Legacy 4G Users: A Game Theoretic Approach

Scalable and Fair Resource Sharing Among 5G D2D Users and Le...

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International Communication Systems and Networks and Workshops, COMSNETS

作者： Sreetama Mukherjee Sasthi C. Ghosh Microsoft R&D Pvt. Ltd. Hyderabad India Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata India

ISBN: (数字)9781728131870

ISBN: (纸本)9781728131887

We propose a game theoretic approach to the problem of resource allocation in 5G device to device (D2D) communications underlaying cellular networks, where modern 5G D2D users (DUs) share channel resources of legacy 4G cellular users (CUs). Though such sharing improves scalability as more and more users can be served, the individual throughput obtained by a CU may get reduced when its channel resource is shared by a DU pair. Thus our aim is to increase the overall system throughput while ensuring effective user fairness among the DUs and CUs served. Our approach provides a tradeoff between the two objectives thereby ensuring no legacy CUs are compromised heavily while encouraging modern DUs. We have addressed this fairness problem by thresholding the reduction of the throughput of a CU with respect to its ideal throughput if not reused. We have proposed a game theoretic model in order to make strategic decision for selecting the preferred action configuration in order to meet this objective. Together with this game model and a validation process, we aim to improve scalability, overall system throughput without compromising on the fairness of the users. We have also compared the user fairness achieved by our approach with an existing approach to demonstrate the effectiveness of our game theoretic approach.

关键词： Copper Throughput Games Resource management Device-to-device communication Interference 5G mobile communication

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Improved bounds on the span of L(1, 2)-edge labeling of some infinite regular grids

arXiv

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arXiv 2022年

作者： Bandopadhyay, Susobhan Ghosh, Sasthi C. Koley, Subhasis School Of Computer Sciences National Institute Of Science Education And Research Bhubaneswar India Advanced Computing And Microelectronics Unit Indian Statistical Institute Kolkata India

For two given nonnegative integers h and k, an L(h, k)-edge labeling of a graph G is the assignment of labels {0, 1,⋯, n} to the edges so that two edges having a common vertex are labeled with difference at least h and two edges not having any common vertex but having a common edge connecting them are labeled with difference at least k. The span λ′h,k(G) is the minimum n such that G admits an L(h, k)-edge labeling. Here our main focus is on finding λ′1,2(G) for L(1, 2)-edge labeling of infinite regular hexagonal (T3), square (T4), triangular (T6) and octagonal (T8) grids. It was known that 7 ≤ λ′1,2(T3) ≤ 8, 10 ≤ λ′1,2(T4) ≤ 11, 16 ≤ λ′1,2(T6) ≤ 20 and 25 ≤ λ′1,2(T8) ≤ 28. Here we settle two long standing open questions i.e. λ′1,2(T3) and λ′1,2(T4). We show λ′1,2(T3) = 7, λ′1,2(T4) = 11. We also improve the bound for T6and T8and prove λ′1,2(T6) ≥ 18, λ′1,2(T8) ≥ 26. © 2022, CC BY.

关键词： Graph theory

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Planarization of metal layers in a chip based on Voronoi diagram

Planarization of metal layers in a chip based on Voronoi dia...

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International Conference on Computers and Devices for Communication (CODEC)

作者： Debasri Saha Susmita Sur-Kolay Department of Computer Sc. and Engineering Indian Institute of Technology Patna India Advanced Computing & Microelectronics Unit Indian Statistical Institute Kolkata India

ISBN: (纸本)9781467326193

Dummy metal fills are inserted in the upper metal layers of a chip to restore planarity of the metal layers and to ensure mechanical robustness of the chip, thereby its performance. Existing tile and window-based metal fill synthesis techniques typically check the metal density of a layer within a square tile window, insert dummy metal shapes in the tile if required, and shift the window by a distance related to the side of the tile to cover the entire layer. As a large number of window positions have to be checked for accuracy, these window based approaches are not efficient. In this paper, we propose a Voronoi diagram-based tessellation for better selection of the positions where metal fills need to be inserted to improve the uniformity criteria. Our method is compared with an existing Monte-Carlo (MC) based fast heuristic using windows on ISCAS'85 benchmarks. Experimental results demonstrate that our method guarantees the same minimum metal density with smaller variation in metal density variation and less coupling capacitance between the metals.

关键词： Chemical-Mechanical Polishing (CMP) uniform metal density area fill synthesis Voronoi Diagram Delaunay Trangulation Voronoi diagrams Metals Tile Computer chips DNA Microarrays PLANARISATION windows window FILL MECHANICAL STRENGTH uniform current density

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Ranking of Optical Character Prototypes in a Large Database Using Isothetic Chord Lengths

Ranking of Optical Character Prototypes in a Large Database ...

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International Conference on computing: Theory and Applications, ICCTA

作者： Partha Bhowmick Arindam Biswas Bhargab B. Bhattacharya Computer Science & Technology Dept Bengal Engineering and Science University Shibpur India Advanced Computing & Microelectronics Unit Indian Statistical Institute Kolkata India

A novel algorithm for conferring a ranking system on the prototypes of a large database of optical/handwritten characters is proposed. The ranking system is designed using the (isothetic) chord lengths of the enclosing isothetic polygons corresponding to the prototypes, for a prescribed grid-size. As the derivation of structural information of a character by thinning or by edge detection is susceptible to its impurity during imaging or post-processing, an isothetic polygon is used that captures the geometric structure of the character in an elegant way. The proposed scheme has a striking potential in deciding the relative merit and usefulness of a particular prototype with respect to the other prototypes of the corresponding character in the concerned database. Several quantitative measures have been suggested, and supporting experimental results have been reported, which justify the strength and efficiency of the proposed method

关键词： Prototypes Spatial databases Optical character recognition software Character recognition Computer science Data engineering Design engineering Optical computing microelectronics Image edge detection

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A cross-layer distributed TDMA scheduling for data gathering with minimum latency in wireless sensor networks

A cross-layer distributed TDMA scheduling for data gathering...

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International Conference on Wireless Communication, Vehicular Technology, Information Theory and Aerospace and Electronic Systems Technology (Wireless VITAE)

作者： Punyasha Chatterjee Nabanita Das Information Technology Department Government College of Engineering and Textile Technology Kolkata India Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata India

In a wireless sensor network, given a routing tree for data gathering from individual nodes to the sink node, this paper presents a simple, distributed algorithm for assigning time slot to each node for conflict-free communication, such that the maximum latency in data gathering at the sink is minimized. It requires just a one-time computation during the initialisation of the network provided the nodes remain static. Simulation studies have been done to evaluate the performance in terms of latency, and the average duty cycle.

关键词： Time division multiple access Delay Wireless sensor networks Access protocols Processor scheduling Computer networks Routing Interference Data communication Energy efficiency

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High performance MCM routing: a new approach

High performance MCM routing: a new approach

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International Conference on VLSI Design

作者： S. Das S.C. Nandy B.B. Bhattacharya Department of Computer Science & Appl. North Bengal University Darjeeling India Advanced Computing & Microelectronics Unit Indian Statistical Institute Calcutta India

In this paper, we present a new approach to MCM routing to minimize the number of vias and wire length. A 3D routing substrate is partitioned into a number of layers. Chip blocks are placed on the top layer, and routing layers are used pair-wise for interconnections. The set of projected pins of the blocks on a routing layer plays the role of obstacles; the space (river) between two consecutive rows/columns of blocks is used for routing. The proposed algorithm consists of a preprocessing stage that determines a routing order among the nets. For each net, a rectilinear Steiner tree with a minimum number of bends is constructed, and the nets are ordered on the basis of a metric called average path length. Next, routing is done in the nonoverlap model, using a heuristic guided by the above ordering. Finally, via minimization is achieved by slightly re-routing the nets in the overlap model. Experimental evidence on standard benchmarks reveals that our solution produces significantly fewer number of vias, and compares favourably with respect to wire length against the best known existing results.

关键词： Routing Wire Integrated circuit interconnections Costs Delay Pins Rivers Minimization Packaging Fabrication

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