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arXiv 2022年

作者： Majumdar, Ritajit Wood, Christopher J. Advanced Computing & Microelectronics Unit Indian Statistical Institute India IBM Quantum IBM T.J. Watson Research Center Yorktown Heights NY10598 United States

We investigate an error mitigated tomographic approach to the quantum circuit cutting problem in the presence of gate and measurement noise. We explore two tomography specific error mitigation techniques;readout error mitigated conditional fragment tomography, which uses knowledge of readout errors on all cut and conditional qubit measurements in the tomography reconstruction procedure;and dominant eigenvalue truncation (DEVT), which aims to improve the performance of circuit cutting by performing truncation of the individual conditional tomography fragments used in the reconstruction. We find that the performance of both readout error mitigated tomography and DEVT tomography are comparable for circuit cutting in the presence of symmetric measurement errors. For gate errors our numerical results show that probability estimates for the original circuit obtained using DEVT outperforms general circuit cutting for measurement, depolarization and weakly biased Pauli noise models, but does not improve performance for amplitude damping and coherent errors, and can greatly decrease performance for highly biased Pauli noise. In cases where DEVT was effective, it as also found to improve performance of partial tomographic reconstruction using at least 50% of the full tomographic data with a conditional least-squares tomographic fitter, while linear inversion tomography with or without DEVT mitigation was found to perform poorly with with partial data. © 2022, CC BY.

关键词： Tomography

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Length-based anchor-free distributed localization in a covered sensor network

Length-based anchor-free distributed localization in a cover...

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International Conference on Wireless Communication and Sensor Networks

作者： B. Sau K. Mukhopadhyaya Kolkata under Faculty Improvement Programme (FIP) University Grant Commission Government of India Jadavpur University India Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata India

ISBN: (纸本)9781424433278

Centralized localization dissipates a lot of energy in pooling the proximity information of the individual nodes. In contrast a distributed algorithm usually uses only local information at each node. Most localization algorithms available in the literature are are anchor based or they estimate the position of the sensors at the cost of losing accuracy. In this paper, we propose an anchor-free length-based distributed localization technique under a restricted model which solves a specialized case of this problem. The model assumes that all known distances between the sensors are less than the communication range of the sensors and all unknown distances are greater. We also assume that communication range is at least twice as much as the sensing range. Every point in the field of interest is assumed to be covered by some sensor. Each sensor localizes some of its neighbours with information from its neighbours. Each node communicates information for localization to its neighbours only; thus reducing traffic over the network. We also show that, the time required to localize all sensors uniquely under this model is linear in the number of sensors.

关键词： Monitoring Wireless sensor networks Network topology Telecommunication traffic Hardware Computer networks Distributed computing microelectronics Mathematics User-generated content

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Sparsity of weighted networks: Measures and applications

arXiv

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arXiv 2020年

作者： Goswami, Swati Das, Asit K. Nandy, Subhas C. Department of Computer Science and Technology Indian Institute of Engineering Science and Technology Shibpur Howrah711103 India Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata700108 India

A majority of real life networks are weighted and sparse. The present article aims at characterization of weighted networks based on sparsity, as a measure of inherent diversity, of different network parameters. It utilizes sparsity index defined on ordered degree sequence of simple networks and derives further properties of this index. The range of possible values of sparsity index of any connected network, with edge-count in specific intervals, is worked out analytically in terms of node-count;a pattern is uncovered in corresponding degree sequences to produce highest sparsities. Given the edge-weight frequency distribution of a network, we have formulated an expression of the sparsity index of edge-weights. Its properties are analyzed under different distributions of edge-weights. For example, the upper and lower bounds of sparsity index of edge-weights of a network, having all distinct edge-weights, is determined in terms of its node-count and edge density. The article highlights that this summary index with low computational cost, computed on different network parameters, is useful to reveal different structural and organizational aspects of networks for performing analysis. An application of this index has been demonstrated through overlapping community detection of networks. The results validated on artificial and real-world networks show its efficacy. Copyright © 2020, The Authors. All rights reserved.

关键词： Population dynamics

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Design of an optimal test pattern generator for built-in self testing of path delay faults

Design of an optimal test pattern generator for built-in sel...

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International Conference on VLSI Design

作者： D.K. Das I. Chaudhuri B.B. Bhattacharya Department of Computer Science & Engineering. Jadavpur University Calcutta India Mentor Graphics Corporation Hyderabad India Advanced Computing & Microelectronics Unit Indian Statistical Institute Calcutta India

A novel design of a test pattern generator (TPG) for built-in self-testing (BIST) of path delay faults, is proposed. For an n-input CUT, the TPG generates a sequence of length (n.2/sup n/+1), that includes all n.2/sup n/ single-input-change (SIC) test pairs, and hence optimal. The generation of such a sequence of minimum length (i.e., n.2/sup n/+1) was an open problem. A simple iterative circuit of the TPG is then constructed. This provides minimum test application time for testing path delay faults, and compares favorably with the earlier BIST designs.

关键词： Test pattern generators Automatic testing Delay Circuit testing Silicon carbide Circuit faults Built-in self-test Electrical fault detection Fault detection Robustness

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Tuning 2D magnetism in Fe3+XGeTe2 films by element doping

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National Science Review 2022年第6期9卷 163-170页

作者： Shanshan Liu Zihan Li Ke Yang Enze Zhang Awadhesh Narayan Xiaoqian Zhang Jiayi Zhu Wenqing Liu Zhiming Liao Masaki Kudo Takaaki Toriyama Yunkun Yang Qiang Li Linfeng Ai Ce Huang Jiabao Sun Xiaojiao Guo Wenzhong Bao Qingsong Deng Yanhui Chen Lifeng Yin Jian Shen Xiaodong Han Syo Matsumura Jin Zou Yongbing Xu Xiaodong Xu Hua Wu Faxian Xiu State Key Laboratory of Surface Physics and Department of Physics Fudan University Institute for Nanoelectronic Devices and Quantum Computing Fudan University College of Science University of Shanghai for Science and Technology Laboratory for Computational Physical Sciences(MOE) Fudan University Solid State and Structural Chemistry Unit Indian Institute of Science School of Electronic Science and Engineering Nanjing University Department of Physics University of Washington Department of Electronic Engineering Royal Holloway University of London Materials Engineering The University of Queensland Beijing Key Laboratory of Microstructure and Property of Advanced Materials Institute of Microstructure and Property of Advanced Materials Beijing University of Technology The Ultramicroscopy Research Center Kyushu University State Key Laboratory of ASIC and System School of Microelectronics Fudan University Collaborative Innovation Center of Advanced Microstructures Department of Applied Quantum Physics and Nuclear Engineering Kyushu University Centre for Microscopy and Microanalysis The University of Queensland Shanghai Research Center for Quantum Sciences

Two-dimensional（2D） ferromagnetic materials have been discovered with tunable magnetism and orbital-driven nodal-line features. Controlling the 2D magnetism in exfoliated nanoflakes via electric/magnetic fields enables a boosted Curie temperature（TC） or phase transitions. One of the challenges, however, is the realization of high TC2D magnets that are tunable, robust and suitable for large scale fabrication. Here, we report molecular-beam epitaxy growth of wafer-scale Fe3+XGeTe2films with TCabove room temperature. By controlling the Fe composition in Fe3+XGeTe2, a continuously modulated TCin a broad range of 185–320 K has been achieved. This widely tunable TCis attributed to the doped interlayer Fe that provides a 40% enhancement around the optimal composition X = 2. We further fabricated magnetic tunneling junction device arrays that exhibit clear tunneling signals. Our results show an effective and reliable approach, i.e. element doping, to producing robust and tunable ferromagnetism beyond room temperature in a large-scale 2D Fe3+XGeTe2fashion.

关键词： 2D ferromagnetic material Fe3+XGeTe2 film element doping above room temperature TC tunability

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A New Look Ahead Technique for Customized Testing in Digital Microfluidic Biochips

A New Look Ahead Technique for Customized Testing in Digital...

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Asian Test Symposium (ATS)

作者： Pranab Roy Hafizur Rahaman Parthasarthi Dasgupta Bhargab B.B. Bhattacharya School of VLSI Technology Bengal Engineering and Science University Shibpur Shibpur India Indian Institute of Management Calcutta India Advanced Computing and Microelectronics Unit Indian Statistical Institute Calcutta India

Digital Micro fluidic biochips have been developed as a promising platform for Lab-on-chip systems that manipulate individual droplet of chemicals on a 2D planar array of electrodes. Due to the significance of the correctness of the results -- fault tolerance and dependability becomes a major issue for operation of these devices. Therefore, such devices are required to be tested frequently both off-line (e.g., post manufacturing) and concurrently ahead of each assay execution. Under both scenarios, testing is accomplished by routing one or more test droplets across the chip simultaneously and recording their arrival at the destination. In this paper we attempted to solve the problem of customized testing for a given Bioassay layout. We have applied a look ahead strategy for parallel testing using multiple droplets for any given test bench with an objective of minimization of test completion time and optimized utilization of test resources. The test simulations are carried out on test benches of Benchmark suite III and results obtained are found to be encouraging.

关键词： Testing Routing Microfluidics Arrays Electrodes Circuit faults Schedules

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Thermal relaxation error on QKD: Effect and A Probable Bypass

arXiv

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arXiv 2022年

作者： Aziz, Munsi Afif Gond, Bishwajit Prasad Nandi, Srijita Ray, Soujanya Bhoumik, Debasmita Majumdar, Ritajit Department of Computer Science & Engineering Government College of Engineering and Leather Technology India National Institute of Technology Sikkim India Advanced Computing & Microelectronics Unit Indian Statistical Institute Kolkata India

Quantum cryptography was proposed as a counter to the capacity of quantum computers to break classical cryptosystems. A broad subclass of quantum cryptography, called quantum key distribution (QKD), relies on quantum mechanical process for secure distribution of the keys. Quantum channels are inherently noisy, and therefore these protocols will be susceptible to noise as well. In this paper, we study the performance of two QKD protocols - BB84 and E91 under thermal relaxation error. We show that while E91 protocol loses its security immediately due to loss of entanglement, the performance of BB84 protocol reduces to random guessing with increasing time. Next, we consider the action of an Eve on the BB84 protocol under thermal relaxation noise, who is restricted to guessing the outcome of the protocol only. Under this restriction, we show that Eve can still do better than random guessing when equipped with the characteristics of the noisy channel. Finally, we propose a modification of the BB84 protocol which retains the security of the original protocol, but ensures that Eve cannot get any advantage in guessing the outcome, even with a complete channel information. Copyright © 2022, The Authors. All rights reserved.

关键词： Quantum cryptography

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Fault Coverage of a Test Set on Structure-Preserving Siblings of a Circuit-Under-Test

Fault Coverage of a Test Set on Structure-Preserving Sibling...

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Asian Test Symposium (ATS)

作者： Manobendra Nath Mondal Animesh Basak Chowdhury Manjari Pradhan Susmita Sur-Kolay Bhargab B. Bhattacharya Advanced Computing & Microelectronics Unit Indian Statistical Institute Kolkata India Centre for Cyber-Security New York University USA Dept. of CSE Indian Institute of Technology Kharagpur India

ISBN: (数字)9781728126951

ISBN: (纸本)9781728126968

Most of the Automatic Test Pattern Generation (ATPG) algorithms for digital circuits rely heavily on netlist description that comprises both network interconnect structure among logic gates and the functionality of each gate. The performance of an ATPG tool on a circuit-under-test (CUT) C is determined by the size of the test set T and its fault coverage (FC). Despite extensive research in the field of testing, the following question remains unanswered: Is the structure or the functionality of C dominant in determining FC of a test-set T for C? In this paper, we present empirical evidence in favour of the dominance of structure on FC by randomly selecting a logic gate from a synthesized netlist for C, and replacing it by a different type of gate. Our experiments provide an un-intuitive result that F C of a test-set T for C under the single stuck-at fault model remains nearly the same on other sibling circuits that have identical structure as of C but with different gate functionality, provided these have similar extent of fault redundancy. This observation supports the view that feeding structural information alone may suffice to train machine-learning models that are currently being used to expedite different problems of digital circuit testing and diagnosis.

关键词： Circuit faults Logic gates Redundancy Sociology Statistics Integrated circuit modeling Tools

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Fault Secured JPEG-Codec Hardware Accelerator with Piracy Detective Control using Secure Fingerprint Template

Fault Secured JPEG-Codec Hardware Accelerator with Piracy De...

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IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

作者： Rahul Chaurasia Abhinav Reddy Asireddy Anirban Sengupta Computer Science and Engineering Indian Institute of Technology Indore India Department of Computer Science and Engineering Indian Institute of Technology Indore Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata India

This paper presents a novel methodology to design fault secured JPEG-compression-decompression (codec) hardware accelerator with piracy detective control using secure fingerprint template of intellectual property (IP) vendor. In the proposed approach, firstly, the fault secured schedule for JPEG-codec design is generated from its behavioral description. Subsequently, in order to enable detective control against piracy, secure digital template corresponding to fingerprint biometric of IP vendor is generated and implanted into the design. In order to do so, firstly, fingerprint features are transformed based on IP vendor specified key-set. Subsequently, the generated secure fingerprint template in the form of encoded hardware security constraints is implanted into the design during behavioral/ high-level synthesis phase of integrated circuit (IC) design. The implanted hardware security constraints thereby ensure the seamless detection and isolation of fake/pirated design versions during piracy detection process, before their conjunction into system on chip (SoC) of electronic systems. The proposed approach achieves the following: i) fault secured hardware accelerator for JPEG-codec with integrated piracy detective control at negligible design cost overhead ii) higher resiliency against tampering attack and iii) lower probability of coincidence (indicating definitive proof of ownership for genuine IP vendor).

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GreyConE: Greybox fuzzing+Concolic execution guided test generation for high level design

arXiv

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arXiv 2022年

作者： Debnath, Mukta Chowdhury, Animesh Basak Saha, Debasri Sur-Kolay, Susmita Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata India Centre for Cybersecurity New York University United States A. K. Choudhury School of It U. of Calcutta India

Exhaustive testing of high-level designs pose an arduous challenge due to complex branching conditions, loop structures and inherent concurrency of hardware designs. Test engineers aim to generate quality test-cases satisfying various code coverage metrics to ensure minimal presence of bugs in a design. Prior works in testing SystemC designs are time inefficient which obstruct achieving the desired coverage in shorter timespan. We interleave greybox fuzzing and concolic execution in a systematic manner and generate quality test-cases accelerating test coverage metrics. Our results outperform state-of-the-art methods in terms of number of test cases and branch-coverage for some of the benchmarks, and runtime for most of them. © 2022, CC BY.

关键词： High level synthesis

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