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作者： Bhowmik, Biswajit Biswas, Santosh Deka, Jatindra Kumar Bhattacharya, Bhargab B. Department of Computer Science and Engineering IIT Guwahati Guwahati781039 India Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata Kolkata700108 India

With the advent of rapidly evolving nanoelectronic systems, compact implementation of versatile and dense network-on-chips (NoCs) on a die has emerged as technology-of-choice for multicore computing. However, because of the increased density, NoCs often suffer from various types of manufacturing faults, which degrade the yield and jeopardize the reliability of the overall system. For example, short-channel faults in an NoC often cause system-level failures that may have significant impact on its performance. This paper proposes a cluster-based distributed scheme for online testing of short faults in NoC channels. The proposed algorithm detects both intra and interchannel short faults and identifies the underlying faulty channel-wires connected to a node. The nodes in a cluster-set are appropriately scheduled to reduce test time. The approach scales to larger NoCs irrespective of size of the network and channel width. The proposed scheme also extends its application from regular to irregular NoCs, and to other channel faults like open. Fault simulation shows that the proposed cluster-driven scheme is capable of detecting all modeled short-channel faults. Online evaluation of the scheme also reveals the extent of impact that the short faults impart on various performance metrics for large traffic. Compared to prior work, it reduces hardware area overhead up to 27% and test time by more than 21 × on several test cases. In addition, packet latency and energy consumption are reduced by 19.47%-40.16% and 17.57%-34.20%, respectively. © 1993-2012 IEEE.

关键词： Network-on-chip

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A Framework for Analyzing Resource Allocation Policies for Multi-Access Edge computing

A Framework for Analyzing Resource Allocation Policies for M...

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IEEE International Conference on Edge computing (EDGE)

作者： Kaustabha Ray Ansuman Banerjee Advanced Computing and Microelectronics Unit Indian Statistical Institute

ISBN: (纸本)9781665400633

Multi-Access Edge computing (MEC) is a promising new paradigm enabling low-latency access to services deployed on edge servers. This helps to avert network latencies often encountered in accessing cloud services. The cornerstone of a MEC environment is a resource allocation policy used to partition and allocate computational resources such as bandwidth, memory available on the edge server to user service invocations availing such services. In this work, we propose a generic data-driven framework to model and analyze such MEC resource allocation policies. We model a MEC system as a Turn-Based Stochastic Multi-Player Game and use Probabilistic Model Checking to derive quantitative guarantees on resource allocation policies against requirements expressed in Probabilistic Alternating-Time Temporal Logic with Rewards. We present results on state-of-the-art MEC resource allocation policies to demonstrate the effectiveness of our framework.

关键词： Analytical models Multi-access edge computing Computational modeling Stochastic processes Games Model checking Probabilistic logic

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One-round discrete voronoi game in R2 in presence of existing facilities 25

One-round discrete voronoi game in R2 in presence of existin...

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25th Canadian Conference on Computational Geometry, CCCG 2013

作者： Banik, Aritra Bhattacharya, Bhaswar B. Das, Sandip Mukherjee, Satyaki Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata India Department of Statistics Stanford University United States Indian Statistical Institute Bangalore India

In this paper we consider a simplified variant of the discrete Voronoi Game in R2, which is also of independent interest in competitive facility location. The game consists of two players P1 and P2, and a finite set U of users in the plane. The players have already placed two sets of facilities F and S, respectively in the plane. The game begins by P1 placing a new facility followed by P2 placing another facility, and the objective of both the players is to maximize their own total payoffs. When |F| = |S| = m, this corresponds to the last round of the (m + 1)-round discrete Voronoi Game in R2. In this paper we propose polynomial time algorithms for obtaining optimal strategies of both the players under arbitrary locations of the existing facilities F and S. We show that the optimal strategy of P2, given any placement of P1, can be found in O(n2) time, and the optimal strategy of P1 can be found in O(n8) time.

关键词： Polynomial approximation

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Isothetic polygonal approximations of a 2D object on generalized grid

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1st International Conference on Pattern Recognition and Machine Intelligence, PReMI 2005

作者： Bhowmick, Partha Biswas, Arindam Bhattacharya, Bhargab B. Computer Science and Technology Department Bengal Engineering and Science University Shibpur Howrah India Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata India

ISBN: (纸本)3540305068

Determination of an isothetic polygonal approximation of the outer or inner contour of an object is a challenging problem with numerous applications to pattern recognition and image processing. In this paper, a novel algorithm is presented for constructing the outer (or inner) tight isothetic polygon(s) containing (or filling) an arbitrarily shaped 2D object on a background grid, using a classical labeling technique, The background grid may consist of uniformly or non-uniformly spaced horizontal and vertical lines. Experimental results for both uniform and non-uniform grids of varying sizes have been reported to demonstrate the applicability and efficiency of the proposed algorithm. © Springer-Verlag Berlin Heidelberg 2005.

关键词： Object recognition

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The p-center problem in tree networks revisited 15

The p-center problem in tree networks revisited

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15th Scandinavian Symposium and Workshops on Algorithm Theory, SWAT 2016

作者： Banik, Aritra Bhattacharya, Binay Das, Sandip Kameda, Tsunehiko Song, Zhao Advanced Computing and Microelectronics Unit Indian Statistical Inst. Kolkata India School of Computing Science Simon Fraser University Vancouver Canada Department of Computer Science University of Texas Austin United States

ISBN: (纸本)9783959770118

We present two improved algorithms for weighted discrete p-center problem for tree networks with n vertices. One of our proposed algorithms runs in O(n log n + p log2 n log(n/p)) time. For all values of p, our algorithm thus runs as fast as or faster than the most efficient O(n log2 n) time algorithm obtained by applying Cole's speed-up technique [10] to the algorithm due to Megiddo and Tamir [20], which has remained unchallenged for nearly 30 years. Our other algorithm, which is more practical, runs in O(n log n + p2 log2 (n/p)) time, and when p = O(√ n) it is faster than Megiddo and Tamir's O(n log2 n log log n) time algorithm [20]. © Aritra Banik, Binay Bhattacharya, Sandip Das, Tsunehiko Kameda, and Zhao Song.

关键词： Forestry

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Fault diagnosis for leakage and blockage defects in flow-based microfluidic biochips

Fault diagnosis for leakage and blockage defects in flow-bas...

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作者： Hu, Kai Bhattacharya, Bhargab B. Chakrabarty, Krishnendu Department of Electrical and Computer Engineering Duke University DurhamNC27708 United States Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata700108 India

Advances in flow-based microfluidics now allow an efficient implementation of biochemistry on-a-chip for DNA sequencing, drug discovery, and point-of-care disease diagnosis. However, the adoption of flow-based biochips is hampered by defects that frequently occur in chips fabricated using soft lithography techniques. Recently published work has shown how we can automate the testing of flow-based biochips;diagnosis methods are now needed to identify the flaws in the fabrication process and to facilitate the use of partially defective chips. Since disposable biochips are being targeted for a highly competitive and low-cost market segment, such diagnosis methods need to be inexpensive, quick, and effective. In this paper, we present the first approach for the automated diagnosis of leakage and blockage defects in flow-based microfluidic biochips. The proposed method targets the identification of fault types and their locations based on test outcomes. It reduces the number of possible fault sites significantly while identifying their exact locations. We use a graph representation of flow paths and a formulation based on hitting sets for the analysis of observed error syndromes. The diagnosis technique is evaluated on three fabricated biochips, and the localization of faults and their classification are achieved correctly in all cases. © 2015 IEEE.

关键词： Biochips

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Exploiting degeneracy to construct good ternary quantum error correcting code

arXiv

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arXiv 2020年

作者： Majumdar, Ritajit Sur-Kolay, Susmita Advanced Computing & Microelectronics Unit Indian Statistical Institute India

Quantum error-correcting code for higher dimensional systems can, in general, be directly constructed from the codes for qubit systems. What remains unknown is whether there exist efficient code design techniques for higher dimensional systems. In this paper, we propose a 7-qutrit error-correcting code for the ternary quantum system and show that this design formulation has no equivalence in qubit systems. This code is optimum in the number of qutrits required to correct a single error while maintaining the CSS structure. This degenerate CSS code can (i) correct up to seven simultaneous phase errors and a single bit error, (ii) correct two simultaneous bit errors on pre-defined pairs of qutrits on eighteen out of twenty-one possible pairs, and (iii) in terms of the cost of implementation, the depth of the circuit of this code is only two more than that of the ternary Steane code. Our proposed code shows that it is possible to design better codes explicitly for ternary quantum systems instead of simply carrying over codes from binary quantum systems. Copyright © 2020, The Authors. All rights reserved.

关键词： Quantum optics

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Approximate Ternary Quantum Error Correcting Code with Low Circuit Cost

Approximate Ternary Quantum Error Correcting Code with Low C...

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International Symposium on Multiple-Valued Logic

作者： Ritajit Majumdar Susmita Sur-Kolay Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata

ISBN: (数字)9781728154060

ISBN: (纸本)9781728154077

Quantum error correcting code (QECC) with encoding and decoding circuits having low gate count, is an important criterion for realizing quantum computing systems. CSS QECCs are known to have simple circuits. Shaw et al. showed that it is not possible to have a 6-qubit CSS type QECC without sharing entanglement between the encoder and the decoder. In this paper, we propose a 6-qutrit approximate QECC (AQECC) of CSS structure which can simultaneously correct phase errors in upto six qutrits, and one bit error in only four of the six qutrits, without sharing prior entanglement. Our AQECC corrects a single error with probability 0.75 for symmetric error model, and probability 0.9988 for asymmetric error model. It also maintains CSS structure without sharing prior entanglement. Furthermore, the quantum cost of a circuit for this AQECC is 55.72% less than that for the 9-qutrit exact QECC. Overall, low qutrit count, low cost circuit realization with low depth and the ability to correct multiple phase errors make our proposed AQECC a suitable candidate for real life quantum channels.

关键词： Cascading style sheets Qubit Encoding Quantum computing Error correction codes Logic gates Error correction

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Homogeneously Representable Interval Bigraphs

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Electronic Notes in Discrete Mathematics 2003年 15卷 75-78页

作者： Das, Sandip Talukdar Malay Sen, P. Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata 700 108 India Dept. of Mathematics University of North Bengal Darjeeling 734 430 West Bengal India

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Special Session: Quantum Error Correction in Near Term Systems

Special Session: Quantum Error Correction in Near Term Syste...

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IEEE International Conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： Ritajit Majumdar Susmita Sur-Kolay Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata

ISBN: (数字)9781728197104

ISBN: (纸本)9781728197111

Large-scale quantum computers mandate error correction and fault tolerance. Due to constraints on the number of qubits, fault tolerance is difficult to achieve in near-term quantum systems. Therefore, error correction should require minimal resources. Gates in the near-term devices are also noisy. Quantum error correction code blocks built with these noisy gates can inject further error in the circuit. The goals for error correction in near-term systems are as follows: (i) using a small number of qubits for encoding, and (ii) keeping cost of circuits for encoding and decoding low. In this paper, we propose two techniques to achieve these mutually orthogonal goals. For a binary quantum system we propose an error estimation method that can aid in reducing the number of error correcting blocks via sparse scheduling. For ternary quantum systems, we propose an approximate code that can correct errors with high probability while significantly reducing the circuit cost. These techniques are expected to be helpful for error mitigation in near-term systems in the absence of fault tolerance.

关键词： Fault tolerance Fault tolerant systems Qubit Logic gates Error correction Error correction codes Noise measurement

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