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作者： Bhowmik, Biswajit Biswas, Santosh Deka, Jatindra Kumar Bhattacharya, Bhargab B. Department of Computer Science and Engineering IIT Guwahati Guwahati781039 India Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata Kolkata700108 India

With the advent of rapidly evolving nanoelectronic systems, compact implementation of versatile and dense network-on-chips (NoCs) on a die has emerged as technology-of-choice for multicore computing. However, because of the increased density, NoCs often suffer from various types of manufacturing faults, which degrade the yield and jeopardize the reliability of the overall system. For example, short-channel faults in an NoC often cause system-level failures that may have significant impact on its performance. This paper proposes a cluster-based distributed scheme for online testing of short faults in NoC channels. The proposed algorithm detects both intra and interchannel short faults and identifies the underlying faulty channel-wires connected to a node. The nodes in a cluster-set are appropriately scheduled to reduce test time. The approach scales to larger NoCs irrespective of size of the network and channel width. The proposed scheme also extends its application from regular to irregular NoCs, and to other channel faults like open. Fault simulation shows that the proposed cluster-driven scheme is capable of detecting all modeled short-channel faults. Online evaluation of the scheme also reveals the extent of impact that the short faults impart on various performance metrics for large traffic. Compared to prior work, it reduces hardware area overhead up to 27% and test time by more than 21 × on several test cases. In addition, packet latency and energy consumption are reduced by 19.47%-40.16% and 17.57%-34.20%, respectively. © 1993-2012 IEEE.

关键词： Network-on-chip

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Fault Coverage of a Test Set on Structure-Preserving Siblings of a Circuit-Under-Test

Fault Coverage of a Test Set on Structure-Preserving Sibling...

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Asian Test Symposium (ATS)

作者： Manobendra Nath Mondal Animesh Basak Chowdhury Manjari Pradhan Susmita Sur-Kolay Bhargab B. Bhattacharya Advanced Computing & Microelectronics Unit Indian Statistical Institute Kolkata India Centre for Cyber-Security New York University USA Dept. of CSE Indian Institute of Technology Kharagpur India

ISBN: (数字)9781728126951

ISBN: (纸本)9781728126968

Most of the Automatic Test Pattern Generation (ATPG) algorithms for digital circuits rely heavily on netlist description that comprises both network interconnect structure among logic gates and the functionality of each gate. The performance of an ATPG tool on a circuit-under-test (CUT) C is determined by the size of the test set T and its fault coverage (FC). Despite extensive research in the field of testing, the following question remains unanswered: Is the structure or the functionality of C dominant in determining FC of a test-set T for C? In this paper, we present empirical evidence in favour of the dominance of structure on FC by randomly selecting a logic gate from a synthesized netlist for C, and replacing it by a different type of gate. Our experiments provide an un-intuitive result that F C of a test-set T for C under the single stuck-at fault model remains nearly the same on other sibling circuits that have identical structure as of C but with different gate functionality, provided these have similar extent of fault redundancy. This observation supports the view that feeding structural information alone may suffice to train machine-learning models that are currently being used to expedite different problems of digital circuit testing and diagnosis.

关键词： Circuit faults Logic gates Redundancy Sociology Statistics Integrated circuit modeling Tools

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Analyzing the Effect of Soft Handover on Handover Performance Evaluation Metrics under Load Condition

Analyzing the Effect of Soft Handover on Handover Performanc...

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作者： Panigrahy, Nitish K. Ghosh, Sasthi C. College of Information and Computer Sciences University of Massachusetts AmherstMA01003-9264 United States Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata700108 India

With increasing popularity of wireless local area network (WLAN) and emerging real-time applications, seamless mobility has become one of the primary concerns. Hence, the choice of a proper handover algorithm is of utmost importance. Various performance evaluation metrics for handover algorithms have been proposed in this regard. We argue that in a multiple access point (AP) scenario, the load on each of the APs, the requested data rate of the mobile terminal, and the soft handover have significant impact on these metrics. In this paper, we present an analytical framework to measure various handover performance evaluation metrics under both load condition and soft handover for a specific data rate request. Our approach is based on finding the circular region centered around an AP within which the requested data rate can be satisfied. We have considered WLAN usage efficiency, handover failure probability, and unnecessary handover probability as evaluation metrics. We have analyzed the impact of load and soft handover on these metrics. The impact of velocity on these metrics has also been analyzed. We also have derived lower bounds on both handover failure probability and unnecessary handover probability by formulating the problem into three circle intersection problem. The circular coverage assumption used in the framework is also validated through simulation. © 1967-2012 IEEE.

关键词： Efficiency

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Innovative ranking strategy for IPL team formation

arXiv

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arXiv 2019年

作者： Banerjee, Saptarshi Mitra, Arnabi Ganguly, Debayan Majumdar, Ritajit Chatterjee, Kingshuk Department of Computer Science and Engineering Government College of Engineering and Leather Technology Advanced Computing & Microelectronics Unit Indian Statistical Institute Kolkata India Department of Computer Science and Engineering Government College of Engineering and Ceramic Technology

Indian Premier League (IPL) is a tournament of twenty over cricket matches. Teams of this tournament are selected via an auction from a pool of players. Each team employs a think-tank to build the best possible team. Few studies have been performed to automate the process of team selection. However, those studies mostly concentrate either on the current form of the players, or their long term performance. In this paper, we have (i) selected traditional features as well as determined some derived features, which are generated from the traditional features, for batsmen and bowlers, (ii) formulated heuristics for clustering batsmen into openers, middle order batsmen and finishers, (iii) formulated heuristics for relative ranking of batsmen and bowlers considering the current performance as well as the experience of each player, and (iv) have proposed two greedy algorithms for team selection where the total credit point of the team and the number of players in each cluster is fixed. Our proposed ranking scheme and algorithm not only determines the best possible team, but can also determine the best alternate player if one of the target players is unavailable. Copyright © 2019, The Authors. All rights reserved.

关键词： Clustering algorithms

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Quantum error-correcting code for ternary logic

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Physical Review A 2018年第5期97卷 052302-052302页

作者： Ritajit Majumdar Saikat Basu Shibashis Ghosh Susmita Sur-Kolay Advanced Computing & Microelectronics Unit Indian Statistical Institute India A.K. Choudhury School of Information Technology University of Calcutta India

Ternary quantum systems are being studied because they provide more computational state space per unit of information, known as qutrit. A qutrit has three basis states, thus a qubit may be considered as a special case of a qutrit where the coefficient of one of the basis states is zero. Hence both (2×2)-dimensional and (3×3)-dimensional Pauli errors can occur on qutrits. In this paper, we (i) explore the possible (2×2)-dimensional as well as (3×3)-dimensional Pauli errors in qutrits and show that any pairwise bit swap error can be expressed as a linear combination of shift errors and phase errors, (ii) propose a special type of error called a quantum superposition error and show its equivalence to arbitrary rotation, (iii) formulate a nine-qutrit code which can correct a single error in a qutrit, and (iv) provide its stabilizer and circuit realization.

关键词： Quantum error correction

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Flow-Based Passive Microfluidic Architecture for Homogeneous Mixing

Flow-Based Passive Microfluidic Architecture for Homogeneous...

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International Symposium on Electronic System Design (ISED)

作者： Tapalina Banerjee Sudip Poddar Robert Wille Bhargab B. Bhattacharya Advanced Computing and Microelectronics Unit Indian Statistical Institute University of Calcutta Kolkata India EDA-LAB National Taiwan University of Science and Technology Taiwan Institute for Integrated Circuits Johannes Kepler University Linz Austria Indian Institute of Technology Kharagpur India

ISBN: (数字)9781728141770

ISBN: (纸本)9781728141787

Accurate sample preparation, an essential component in microfluidic design automation, poses a great challenge to lab-on-chip (LoC) designers. Although continuous-flow based microfluidic biochips (CFMBs) offer many advantages, the problem of achieving fast, stable, and controllable sample concentration becomes more pronounced when such chips are used. Most of the flow-based dilutions and/or mixing methods need certain settling time to ensure an output flow with stable concentration profile resulting in initial loss of fluids. Control-valve sequencing along with time management for injecting input fluids further complicates the scenario. In this paper, we address the problem of preparing a homogeneous mixture of several input-fluids with different concentration factors. We present a binary tree-based free-flowing microfluidic architecture, which obviates the need for any control valve. The passive fluidic network supports balanced hydraulic resistance along all input-output fluid paths and ensures low Reynolds number. We show that the homogeneity of mixing can be expedited by properly assigning inlets to fluids with different concentrations based on a graph-matching algorithm. The method reveals how design automation tools can be effectively used for solving a problem of fluid dynamics. Theoretical attributes of the proposed architecture, when compared with COMSOL Multiphysics based simulations, provide excellent agreement with high accuracy.

关键词： Mixers Valves Computer architecture Immune system Computer science

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A synoptic study on fault testing in reversible and quantum circuits 1st

A synoptic study on fault testing in reversible and quantum ...

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1st International Conference on Algorithms and Applications, ALAP 2018

作者： Dey, Ramyadeep Bandyopadhyay, Paramita Chandra, Somenath Majumdar, Ritajit Department of Computer Science & Engineering B. P. Poddar Institute of Management & Technology Maulana Abul Kalam Azad University of Technology Kolkata India Advanced Computing & Microelectronics Unit Indian Statistical Institute Kolkata India

ISBN: (纸本)9789811081019

Reversible computation, whose special class is quantum computation, arises from the desire to reduce power dissipation, which can be zero under ideal physical circumstances. Nowadays, error correction and fault testing are of utmost importance for the physical implementation of reversible and quantum circuits in a noisy environment. In this paper, we review various fault models in reversible and quantum circuits. In classical reversible circuits, we review (i) test pattern generation for Single Missing Gate Fault (SMGF), Partial Missing Gate Fault (PMGF), and Multiple Missing Gate Fault (MMGF) models and (ii) show that Universal Test Set (UTS) can be used to detect any of these faults. However, classical fault models do not capture all the logical failures found in quantum circuits. In quantum circuits, we review (i) depolarizing faults, initialization inaccuracy and measurement inaccuracy, and (ii) give some remedial strategies to deal with these fault models. Finally, we show that for a special class of quantum operators, detection of SMGF is sufficient to detect fault due to multiple occurrences of the gate also. Further, we argue with an example that it may not be possible to generate test patterns to detect any arbitrary SMGF in a quantum circuit. © Springer Nature Singapore Pte Ltd. 2018.

关键词： Error correction

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Secure multipath routing for multimedia communication in cognitive radio networks

Secure multipath routing for multimedia communication in cog...

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作者： Bhattacharya, Ansuman Ghosh, Sasthi C. Sinha, Koushik Sinha, Bhabani P. Department of Computer Science and Engineering National Institute of Technology Meghalaya Shillong India Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata West Bengal India Department of Computer Science Southern Illinois University CarbondaleIL United States

In this paper, a novel technique for secure multihop communication in cognitive radio networks is proposed which allows the use of non-contiguous channels for communication of multimedia data without compromising the desired QoS. This technique first creates a number of sub-packets formed by suitably shuffling the bits of the original packet, finds multiple routes by executing the max-flow algorithm on a derivative of the network graph to meet the required bandwidth, suitably allocates channels for each hop in the multiple paths using the features of cognitive radio networks, and sends the sub-packets along these channels which are received by the destination node to form the original packet. This strategy also leads to significantly enhanced security of the data packets against the eavesdropping attack when multiple node-disjoint paths are chosen for transmitting the sub-packets. Copyright © 2018 Inderscience Enterprises Ltd.

关键词： Frequency division multiple access

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Performance-aware test scheduling for diagnosing coexistent channel faults in topology-agnostic networks-on-chip

Performance-aware test scheduling for diagnosing coexistent ...

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作者： Bhowmik, Biswajit Kumar Deka, Jatindra Biswas, Santosh Bhattacharya, Bhargab B. Department of Computer Science and Engineering Indian Institute of Information Technology Kurnool Jagannathagattu Hill Kurnool Andhra Pradesh518007 India Department of Computer Science and Engineering Indian Institute of Technology Guwahati Amingaon Kamrup Guwahati Assam781039 India Department of Electrical Engineering and Computer Science Indian Institute of Technology Bhilai GEC Campus Sejbahar Raipur Chhattisgarh492015 India Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata 203 B. T. Road Kolkata West Bengal700108 India

High-performance multiprocessor SoCs used in practice require a complex network-on-chip (NoC) as communication architecture, and the channels therein often suffer from various manufacturing defects. Such physical defects cause a multitude of system-level failures and subsequent degradation of reliability, yield, and performance of the computing platform. Most of the existing test approaches consider mesh-based NoC channels only and do not perform well for other regular topologies such as octagons or spidergons, with regard to test time and overhead issues. This article proposes a topology-agnostic test mechanism that is capable of diagnosing on-line, coexistent channel-short, and stuck-at faults in these special NoCs as well as in traditional mesh architectures. We introduce a new test model called Damaru to decompose the network and present an efficient scheduling scheme to reduce test time without compromising resource utilization during testing. Additionally, the proposed scheduling scheme scales well with network size, channel width, and topological diversity. Simulation results show that the method achieves nearly 92% fault coverage and improves area overhead by almost 60% and test time by 98% compared to earlier approaches. As a sequel, packet latency and energy consumption are also improved by 67.05% and 54.69%, respectively, and they are further improved with increasing network size. © 2019 Association for computing Machinery.

关键词： Network-on-chip

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An automata theoretic framework for detecting schedulability attacks on cyber-physical systems

An automata theoretic framework for detecting schedulability...

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International Conference on Emerging Applications of Information Technology (EAIT)

作者： Debleena Das Ansuman Banerjee Sandeep K. Shukla Department of Computer Science and Engineering Indian Institute of Technology Kanpur Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata

This paper proposes an automated framework for detecting schedulability attacks on CyberPhysical systems (CPS) that lead to loss of control performance. Given a set of control components that constitute a CPS, a control objective to be satisfied by the control ensemble, the question of schedulability and synthesis of a scheduler that can ensure the desired control performance has been recently studied in literature. In this paper, we extend this idea further to build an automata theoretic framework for assessment of attacks on schedulability. We have built an end-to-end framework that takes in a set of control components, their variants (after replacement), a control objective to be guaranteed, and performs an automated schedulability assessment. We report some preliminary experiments of our framework on simple benchmarks.

关键词： Automata Schedules Scheduling Cyber-physical systems Cyberattack Task analysis

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