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IEEE Computer Society Annual Symposium on VLSI

作者： Sabyasachee Banerjee Subhashis Majumder Bhargab B. Bhattacharya Department of Computer Science and Engineering Heritage Institute of Technology Kolkata Advanced Computing & Microelectronics Unit Indian Statistical Institute Kolkata

Netlist partitioning is an important part of the physical design of 3D IC chips. Each subcircuit corresponding to a partition is subsequently assigned to a suitable device layer in the design phase. This paper proposes a netlist partitioning technique that intends to minimize the number of inter-layer interconnections while maintaining the area constraints. This, in turn, will minimize the area and cost associated with the Through-Silicon Vias (TSVs) needed in the design. The proposed method starts with an BFS-based initial solution and then improves iteratively using a heuristic. Experimental results demonstrate that by reassigning some modules to other layers, our algorithm could achieve up to 45% reduction in the number of TSVs on several benchmark circuits compared to earlier approaches. The resulting increase in floor area due to movement of modules a cross layers, is almost compensated by the decrease in TSV-area. Thus while satisfying the area-constraints, it allows us to reduce the number of TSVs as well as the IR-drop and delay associated with the vias.

关键词： Partitioning algorithms Three-dimensional displays Through-silicon vias Algorithm design and analysis Benchmark testing Time complexity

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A thermal and congestion driven global router for 3D integrated circuits

A thermal and congestion driven global router for 3D integra...

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IEEE Students' Technology Symposium (TechSym)

作者： Debashri Roy Prasun Ghosal Nabanita Das Department of IT Bengal Engineering and Science University Shibpur Howrah WB INDIA Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata WB INDIA

During recent days, the large problem space of very large scale integrated (VLSI) circuits has led global routing problem to a NP Complete one. With the advent of three dimensional integrated circuits (3D IC) the problem has become more complex. In this paper, a multi-objective global routing technique is formulated using fuzzy logic to get rid of the limitations of deterministic approaches. During global routing the decision is taken from a fuzzy logic expert system depending upon some generated pre-routing guiding information. Proposed approach is mainly focused on the modern generation 3D ICs. This primary work is mainly incorporated in the standard cell design for 3D ICs. A two-pin global router tool is designed based on the proposed algorithm resulting 85-97% routability in negligible time for ISPD'98 benchmarks.

关键词： Routing Three-dimensional displays Expert systems Benchmark testing Integrated circuits Sensitivity Fuzzy logic

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Interference Avoidance through Frequency Assignment and Association Control in IEEE 802.11 WLAN

Interference Avoidance through Frequency Assignment and Asso...

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IEEE International Symposium on Network computing and Applications

作者： Babul P. Tewari Sasthi C. Ghosh Department of Computer Science & Engineering Dr. B. C. Roy Engineering College Durgapur West Bengal India Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata India

Very often a denser deployment of APs is required to increase the coverage and capacity in IEEE 802.11 WLAN. It increases the number of APs with overlapping coverage areas. Such overlapping eventually makes more and more clients to fall in the common coverage area of several APs. Interfering APs require different frequency channels for operation in order to avoid the co-channel interference between the APs. Two clients receiving down-link data from two non-interfering APs operating on the same frequency, may also suffer from interference, if both the clients present within the intersecting coverage area of their associating APs. This type of client interference is very common, as the number of available frequency channels is very limited. Ignorance of both types of interference may significantly overestimates the network performance while independent consideration of the frequency assignment and the association control to deal with such interferences, may lead to a sub-optimal solution. In this paper we argue that both the frequency assignment and the association control play an important role and they should be considered simultaneously to improve the overall network performance. We propose an efficient greedy algorithm that jointly deals with the frequency assignment and association control to maximize the aggregate down-link throughput while avoiding both type of interferences. Through simulation, we have shown that our proposed approach is superior than both the traditional approach of dealing with these interferences and the approach that ignores these interferences altogether.

关键词： Throughput Aggregates IEEE 802.11 Standards Frequency control Interchannel interference Channel allocation

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Almost Empty Monochromatic Triangles in Planar Point Sets

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Electronic Notes in Discrete Mathematics 2013年 44卷 53-59页

作者： Basu, Deepan Bhattacharya, Bhaswar B. Das, Sandip Indian Statistical Institute Kolkata India Department of Statistics Stanford University California United States Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata India

For positive integers c, s≥1, let M3(c, s) be the smallest integer such that any set of at least M3(c, s) points in the plane, no three on a line, and colored with c colors, contains a monochromatic triangle with at most s interior points. The case s=0, which corresponds to empty monochromatic triangles, has been studied extensively over the last few years. In particular, it is known that M3(1, 0)=3, M3(2, 0)=9 and M3(c, 0)=∞, for c≥3. In this paper, we prove that the smallest integer λ3(c) such that M3(c, λ3(c))<∞ is bounded above by c-2. We show this by proving M3(c, c-2)≤(c+1)², for c≥2. We also determine the exact values of M3(c, s) for small values of c and s. © 2013 Elsevier B.V.

关键词： Combinatorial convexity Discrete geometry Empty polygons Erdos-Szekeres theorem

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Two-round discrete voronoi game along a line

Two-round discrete voronoi game along a line

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7th International Frontiers in Algorithmics Workshop and the 9th International Conference on Algorithmic Aspects in Information and Management, FAW-AAIM 2013

作者： Banik, Aritra Bhattacharya, Bhaswar B. Das, Sandip Das, Sreeja Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata India Department of Statistics Stanford University United States Jadavpur University Kolkata India

ISBN: (纸本)9783642387555

The two-round discrete Voronoi game on a line consists of a finite user set U (with |U | = n), placed along a line , and two players Player 1 (P1) and Player 2 (P2). We assume that the sorted order of users in U along the line is known, and P1 and P2 each has two facilities. P1 places one facility followed by which P2 places another facility and this continues for two rounds. The payoff of P2 is defined as the cardinality of the set of points in U which are closer to a facility owned by P2 than to every facility owned by P1. The payoff of P1 is the number of users in U minus the payoff of P2. The objective of both the players is to maximize their respective payoffs. In this paper we show that, P2 always gets at least n/2 users, i.e., P2 always wins the game and the bound is tight. We also present efficient algorithms to find the optimal strategies of the players in both the rounds. © 2013 Springer-Verlag Berlin Heidelberg.

关键词： Computers

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One-round discrete voronoi game in R2 in presence of existing facilities 25

One-round discrete voronoi game in R2 in presence of existin...

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25th Canadian Conference on Computational Geometry, CCCG 2013

作者： Banik, Aritra Bhattacharya, Bhaswar B. Das, Sandip Mukherjee, Satyaki Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata India Department of Statistics Stanford University United States Indian Statistical Institute Bangalore India

In this paper we consider a simplified variant of the discrete Voronoi Game in R2, which is also of independent interest in competitive facility location. The game consists of two players P1 and P2, and a finite set U of users in the plane. The players have already placed two sets of facilities F and S, respectively in the plane. The game begins by P1 placing a new facility followed by P2 placing another facility, and the objective of both the players is to maximize their own total payoffs. When |F| = |S| = m, this corresponds to the last round of the (m + 1)-round discrete Voronoi Game in R2. In this paper we propose polynomial time algorithms for obtaining optimal strategies of both the players under arbitrary locations of the existing facilities F and S. We show that the optimal strategy of P2, given any placement of P1, can be found in O(n2) time, and the optimal strategy of P1 can be found in O(n8) time.

关键词： Polynomial approximation

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25th Annual Computational Neuroscience Meeting CNS-2016, Seogwipo City, South Korea, July 2-7, 2016 Abstracts

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BMC NEUROSCIENCE 2016年第1期17卷 1-112页

作者： [Anonymous] Computational Neurobiology Laboratory The Salk Institute for Biological Studies San Diego USA UNIC CNRS Gif sur Yvette France The European Institute for Theoretical Neuroscience (EITN) Paris France ATR Computational Neuroscience Laboratories Kyoto Japan Krembil Research Institute University Health Network Toronto Canada Department of Physiology University of Toronto Toronto Canada Department of Medicine (Neurology) University of Toronto Toronto Canada Department of Physics University of New Hampshire Durham USA Department of Neurophysiology Nencki Institute of Experimental Biology Warsaw Poland Department of Theory Wigner Research Centre for Physics of the Hungarian Academy of Sciences Budapest Hungary Department of Mathematical Sciences KAIST Daejoen Republic of Korea Department of Mathematics University of Houston Houston USA Department of Biochemistry & Cell Biology and Institute of Biosciences and Bioengineering Rice University Houston USA Department of Biology and Biochemistry University of Houston Houston USA Grupo de Neurocomputación Biológica Dpto. de Ingeniería Informática Escuela Politécnica Superior Universidad Autónoma de Madrid Madrid Spain Department of Biological Sciences University of Southern California Los Angeles USA Center for Neuroscience Korea Institute of Science and Technology Seoul South Korea Department of Neurology Albert Einstein College of Medicine Bronx USA Center for Neuroscience KIST Seoul South Korea Department of Neuroscience University of Science and Technology Daejon South Korea Systems Neuroscience Group QIMR Berghofer Medical Research Institute Herston Australia Department of Psychology Yonsei University Seoul South Korea Department of Psychiatry Kyung Hee University Hospital at Gangdong Seoul South Korea Department of Psychiatry Veterans Administration Boston Healthcare System and Harvard Medical School Brockton USA Department of Electrical and Electronic Engineering The University of Melbourne Parkvil

A1 Functional advantages of cell-type heterogeneity in neural circuits Tatyana O. Sharpee A2 Mesoscopic modeling of propagating waves in visual cortex Alain Destexhe A3 Dynamics and biomarkers of mental disorders Mitsuo Kawato F1 Precise recruitment of spiking output at theta frequencies requires dendritic h-channels in multi-compartment models of oriens-lacunosum/moleculare hippocampal interneurons Vladislav Sekulić, Frances K. Skinner F2 Kernel methods in reconstruction of current sources from extracellular potentials for single cells and the whole brains Daniel K. Wójcik, Chaitanya Chintaluri, Dorottya Cserpán, Zoltán Somogyvári F3 The synchronized periods depend on intracellular transcriptional repression mechanisms in circadian clocks. Jae Kyoung Kim, Zachary P. Kilpatrick, Matthew R. Bennett, Kresimir Josić O1 Assessing irregularity and coordination of spiking-bursting rhythms in central pattern generators Irene Elices, David Arroyo, Rafael Levi, Francisco B. Rodriguez, Pablo Varona O2 Regulation of top-down processing by cortically-projecting parvalbumin positive neurons in basal forebrain Eunjin Hwang, Bowon Kim, Hio-Been Han, Tae Kim, James T. McKenna, Ritchie E. Brown, Robert W. McCarley, Jee Hyun Choi O3 Modeling auditory stream segregation, build-up and bistability James Rankin, Pamela Osborn Popp, John Rinzel O4 Strong competition between tonotopic neural ensembles explains pitch-related dynamics of auditory cortex evoked fields Alejandro Tabas, André Rupp, Emili Balaguer-Ballester O5 A simple model of retinal response to multi-electrode stimulation Matias I. Maturana, David B. Grayden, Shaun L. Cloherty, Tatiana Kameneva, Michael R. Ibbotson, Hamish Meffin O6 Noise correlations in V4 area correlate with behavioral performance in visual discrimination task Veronika Koren, Timm Lochmann, Valentin Dragoi, Klaus Obermayer O7 Input-location dependent gain modulation in cerebellar nucleus neurons Maria Psarrou, Maria Schilstra, Neil Davey, Benjamin Torben-Ni

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A combined frequency assignment and AP scheduling for throughput maximization in IEEE 802.11 WLAN 13

A combined frequency assignment and AP scheduling for throug...

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11th International Conference on Advances in Mobile computing and Multimedia, MoMM 2013

作者： Tewari, Babul P. Ghosh, Sasthi C. Department of Computer Science and Engineering Bengal College of Engineering and Technology Durgapur 713 212 West Bengal India Advanced Computing and Microelectronics Unit Indian Statistical Institute 203 B. T. Road Kolkata 700 108 India

ISBN: (纸本)9781450321068

Frequency channels are allocated to the access-points (APs) satisfying the co-channel interference in an IEEE 802.11 WLAN. Very few APs can be activated simultaneously with a conflict-free frequency assignment to them, due to limited number of frequencies. This may lead to a reduced aggregate throughput. We argue that aggregate throughput can significantly be improved by allowing some of the selected interfering APs to be activated with the same frequency but to operate in a fairly time-scheduled manner to satisfy the co-channel interference. We introduce the notion of class and cluster and based on it propose a combined frequency assignment, AP scheduling and association algorithm with the objective of maximizing the aggregate throughput. Simulation results show that the proposed algorithm is superior than both the algorithms that ignores the co-channel interference altogether by assuming proper frequency planning and that allows to activate only those APs for which a conflict-free frequency assignment exists. © 2013 ACM.

关键词： Scheduling

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Updation of Activation Sequence of a Chip after its Deployment for Access Control

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Procedia Technology 2013年 10卷 373-380页

作者： Debasri Saha Susmita Sur-Kolay A. K. Choudhury School of Information Technology University of Calcutta Kolkata-700009 India Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata-700108 India

For protection of Intellectual Property (IP) in VLSI industry, a design level obfuscation is applied for simultaneous authentication and locking of IPs. When a chip with multiple IPs or System-on-Chip (SoC) is deployed, application of the same input sequence each time for its activation encourages interception/tapping of the sequence and subsequent breach of security. A legal user may sell the hardware and share its secret information for activation. Therefore, periodic update of activation sequence of a chip/SoC is a practical requirement. However, update of activation sequence is not supported in an IC. We propose a low overhead, low complexity design modification to facilitate periodic as well as on-demand update of activation sequence of a chip/SoC after its deployment. For the proposed technique, the probability of predicting an updated sequence from its correlation with the previous ones is negligible for an attacker. The simulation results on ISCAS’89 benchmark circuits are encouraging. The overheads of design modification on area, delay and power are very low.

关键词： Intellectual property protection finite state machine obfuscation key-based locking interception access control

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Impact of Inductance on the Performance of Single Walled Carbon Nanotube Bundle Interconnects

Impact of Inductance on the Performance of Single Walled Car...

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International Symposium on Electronic System Design (ISED)

作者： Manodipan Sahoo Hafizur Rahaman Bhargab Bhattacharya Department of Information Technology Bengal Engineering & Science University Shibpur Howrah India Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata India

In this work, we have studied the inductive properties of interconnects built with Single Walled Carbon Nan tube (SWCNT) bundle. We have used the most recent ITRS-2011 data while estimating the RLC parameters of SWCNT bundle interconnects. In our analysis, we have used the classical ABCD-parameter-matrix based method and a delay allowance of 50%. Simulations are performed for both sparse and dense SWCNT bundle interconnects at 21 nm and 15 nm technology nodes, considering three levels of their application: local, intermediate, and global. It is observed that for a 100 MHz periodic square wave input with a rise time of 10 ps, SWCNT bundle interconnects are not impacted by inductance. It is shown that for the given input signal and SWCNT bundle parameters, the length over which the inductive effects will be more prominent, has little practical significance. It is quantitatively shown that the inductive effects will mostly impact the long-intermediate and global interconnects. With technology scaling, such effects may worsen the performance. It is also observed that the Elmore-based methodology for delay estimation of SWCNT bundle interconnects predicts the actual delay very accurately with a maximum error of only 5.46%.

关键词： Inductance Delays Integrated circuit interconnections Resistance Quantum capacitance Carbon nanotubes

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