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A Generalized Theory for Formal Assertion Coverage

A Generalized Theory for Formal Assertion Coverage

引用

Asian Test Symposium (ATS)

作者： Sourasis Das Ansuman Banerjee Pallab Dasgupta Department of Computer Science and Engineering IIT Kharagpur India Advanced Computing and Microelectronics Unit Indian Statistical Institute India

Coverage of formal property specifications has important ramifications in design verification. Mutation coverage, a well studied approach towards specification coverage, checks whether the specification fails in the presence of a fault. Existing mutation coverage methods are broadly divided into those which inject the fault into a given implementation and those which inject the fault directly into the specification. This paper presents a theory which unifies these contrasting approaches and extends the mutation coverage approach to partial implementations where some components are given, and for the others, we only have component specifications.

关键词： Topology Cost accounting Standards Protocols Performance evaluation microelectronics Computer bugs

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Algorithms for On-Chip Solution Preparation Using Digital Microfluidic Biochips

Algorithms for On-Chip Solution Preparation Using Digital Mi...

引用

IEEE Computer Society Annual Symposium on VLSI

作者： Sudip Roy Partha P. Chakrabarti Bhargab B. Bhattacharya Department of Computer Science and Engineering Indian Institute of Technology Kharagpur India Advanced Computing and Microelectronics Unit ISI Kolkata India

Digital micro fluidic (DMF) biochips have recently emerged as a very new technology for health-care and biochemical laboratory applications, as they are inexpensive, sensitive, fully-automated, integrated systems. In a DMF biochip, on-chip and automatic solution preparation requires solving of some algorithmic problems. In this paper, we present some results of our proposed algorithms for on-ship solution preparation using DMF biochips.

关键词： Design automation Optimization System-on-a-chip Laboratories Electrodes Reservoirs Mixers

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Joint frequency assignment and optimal association of stations to access points in IEEE 802.11 WLAN 12

Joint frequency assignment and optimal association of statio...

引用

15th ACM International Conference on Modeling, Analysis and Simulation of Wireless and Mobile Systems, MSWiM 2012

作者： Tewari, Babul P. Ghosh, Sasthi C. Department of Computer Science and Engineering NSHM Knowledge Campus Durgapur Group of Institutions Durgapur 713 212 West Bengal India Advanced Computing and Microelectronics Unit Indian Statistical Institute 203 B. T. Road Kolkata-700 108 West Bengal India

ISBN: (纸本)9781450316286

Frequency channels are allocated to the access-points (APs) subject to an acceptable co-channel interference level in an IEEE 802.11 WLAN. Due to limited number of the non- overlapping frequency channels, all APs in a given area may not be activated simultaneously. Therefore which subset of the APs to select for activation is a major concern. Given a set of selected APs, often a station (STA) can potentially associate with more than one AP. The association of an STA to an inappropriate AP will not only lead to degraded service for the concern STA but also may pull down the throughput of the other STAs associated with that AP. Thus finding the optimal association between STAs and APs is another im- portant concern. We argue that treating these two issues in succession may lead to suboptimal solutions, whereas, ignor- ing the co-channel interference may result over estimation of the throughput. In this paper, an integrated model based on integer programming and an efficient greedy algorithm are proposed that address both aspects simultaneously and maximizes the overall throughput while taking care of load balancing across different APs. Computational results show that indeed the integrated approach is superior to both two- step approach and methods that ignore the interference.

关键词： Integer programming

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Approximation algorithms for deployment of sensors for line segment coverage in wireless sensor networks

Approximation algorithms for deployment of sensors for line ...

引用

International Communication Systems and Networks and Workshops, COMSNETS

作者： Dinesh Dash Arijit Bishnu Arobinda Gupta Subhas C. Nandy Department of Computer Science & Engineering Indian Institute of Technology Kharagpur India Advanced Computing and Microelectronics Unit Indian Statistical Institute India

The coverage problem in wireless sensor network deals with the problem of covering a region or parts of it with sensors. In this paper, we address the problem of covering a set of line segments with minimum number of sensors. A line segment ℓ is said to be 1-covered if it intersects the sensing region of at least one among the sensors distributed in a bounded rectangular region R. We assume that the sensing radius of each sensor is uniform. The problem of finding the minimum number of sensors needed to 1-cover each member in a given set of line segments in R is NP-hard. We propose two constant factor approximation algorithms and a PTAS (Polynomial Time Approximation Scheme) for the problem for 1-covering a set of axis-parallel line segments. We also show that a PTAS exists for 1-covering a set of arbitrarily oriented line segments in R where the length of the line segments are bounded within a constant factor of the sensing radius of each sensor.

关键词： Sensors Approximation methods Strips Approximation algorithms Wireless sensor networks Roads Complexity theory

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Planarization of metal layers in a chip based on Voronoi diagram

Planarization of metal layers in a chip based on Voronoi dia...

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International Conference on Computers and Devices for Communication (CODEC)

作者： Debasri Saha Susmita Sur-Kolay Department of Computer Sc. and Engineering Indian Institute of Technology Patna India Advanced Computing & Microelectronics Unit Indian Statistical Institute Kolkata India

ISBN: (纸本)9781467326193

Dummy metal fills are inserted in the upper metal layers of a chip to restore planarity of the metal layers and to ensure mechanical robustness of the chip, thereby its performance. Existing tile and window-based metal fill synthesis techniques typically check the metal density of a layer within a square tile window, insert dummy metal shapes in the tile if required, and shift the window by a distance related to the side of the tile to cover the entire layer. As a large number of window positions have to be checked for accuracy, these window based approaches are not efficient. In this paper, we propose a Voronoi diagram-based tessellation for better selection of the positions where metal fills need to be inserted to improve the uniformity criteria. Our method is compared with an existing Monte-Carlo (MC) based fast heuristic using windows on ISCAS'85 benchmarks. Experimental results demonstrate that our method guarantees the same minimum metal density with smaller variation in metal density variation and less coupling capacitance between the metals.

关键词： Chemical-Mechanical Polishing (CMP) uniform metal density area fill synthesis Voronoi Diagram Delaunay Trangulation Voronoi diagrams Metals Tile Computer chips DNA Microarrays PLANARISATION windows window FILL MECHANICAL STRENGTH uniform current density

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A New Look Ahead Technique for Customized Testing in Digital Microfluidic Biochips

A New Look Ahead Technique for Customized Testing in Digital...

引用

Asian Test Symposium (ATS)

作者： Pranab Roy Hafizur Rahaman Parthasarthi Dasgupta Bhargab B.B. Bhattacharya School of VLSI Technology Bengal Engineering and Science University Shibpur Shibpur India Indian Institute of Management Calcutta India Advanced Computing and Microelectronics Unit Indian Statistical Institute Calcutta India

Digital Micro fluidic biochips have been developed as a promising platform for Lab-on-chip systems that manipulate individual droplet of chemicals on a 2D planar array of electrodes. Due to the significance of the correctness of the results -- fault tolerance and dependability becomes a major issue for operation of these devices. Therefore, such devices are required to be tested frequently both off-line (e.g., post manufacturing) and concurrently ahead of each assay execution. Under both scenarios, testing is accomplished by routing one or more test droplets across the chip simultaneously and recording their arrival at the destination. In this paper we attempted to solve the problem of customized testing for a given Bioassay layout. We have applied a look ahead strategy for parallel testing using multiple droplets for any given test bench with an objective of minimization of test completion time and optimized utilization of test resources. The test simulations are carried out on test benches of Benchmark suite III and results obtained are found to be encouraging.

关键词： Testing Routing Microfluidics Arrays Electrodes Circuit faults Schedules

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Validation of a DiffServ based QoS model implementation for real-time traffic in a test bed

Validation of a DiffServ based QoS model implementation for ...

引用

National Conference on Communications (NCC)

作者： Sruti Gan Chaudhuri C. S. Kumar Ratnam V. RajaKumar Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata India Department of Mechanical Engineering Indian Institute of Technology Kharagpur India Department of Electronics and Electrical Communication Engineering Indian Institute of Technology Kharagpur India

This paper presents a DiffServ based adaptive QoS model for real-time interactive traffic in constrained bandwidth IP network without over provisioning the users. A WRR based QoS scheduling algorithm has been implemented to allocate the network resources to the users. A tuning parameter for VBR real-time traffic is also introduced in order to provide fair performance to the non real-time traffic as well. The QoS model is implemented at the transmitter edge of the network. Edge switches and routers are configured with the proposed algorithm. The simulation (using NS2) and experimental results (using a test bed with real time network scenario) are presented for validation of the proposed model.

关键词： Quality of service Real time systems Bandwidth Diffserv networks Delay Streaming media Adaptation models

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Requirement Evolution Management: A Systematic Approach

Requirement Evolution Management: A Systematic Approach

引用

IEEE Computer Society Annual Symposium on VLSI

作者： Ansuman Banerjee Advanced Computing and Microelectronics Unit Indian Statistical Institute India

Evolution of requirements is a natural phenomenon in the development life cycle of both software and hardware systems. As requirements evolve, new features are added and existing features are modified or deleted. To conform to the requirement evolution, the current working version of the implementation also has to change in most cases, to support the changed needs. In this paper, we propose an automated approach for analyzing and debugging requirement evolutions. Given two requirements (a reference one and a new, modified one) and a design implementation that conforms to the earlier requirement, our approach uses symbolic specification comparison and unfolding to extract the unsupported requirement core. In addition, to aid the programmer, our method also synthesizes a set of scenarios that may aid the developer address the changed requirements.

关键词： Cost accounting Debugging Systematics Data structures Computer bugs Protocols Synthesizers

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Special issue on selected papers from the third annual workshop on algorithms and computation (WALCOM 2009)

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Journal of Graph Algorithms and Applications 2011年第3期15卷 319-321页

作者： Das, Sandip Uehara, Ryuhei Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata 700 108 India Asahidai 1-1 Ishikawa 923-1292 Japan

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Backward Reasoning with Formal Properties: A Methodology for Bug Isolation on Simulation Traces

Backward Reasoning with Formal Properties: A Methodology for...

引用

Asian Test Symposium (ATS)

作者： Anvesh Komuravelli Srobona Mitra Ansuman Banerjee Pallab Dasgupta Department of Computer Science & Engineering Indian Institute of Technology Kharagpur India Advanced Computing and Microelectronics Unit Indian Statistical Institute India

Automated methods for bug localization for hardware designs typically work on the design implementation to root-cause a given bug. This paper presents a novel debugging approach where instead of using the design implementation in the debugging process, we use causal deduction using formal properties scattered across the design to locate the bug. This has two advantages, namely, (a) the reasoning takes place in the property space instead of the state space of the implementation, which enhances scalability, and (b) new properties can be added in hindsight to perform what-if analysis, which is less expensive than modifying the implementation for each alternative. Experimental results demonstrate the scalability of the approach in debugging designs with large property suites.

关键词： Debugging Cognition Cost accounting Scalability Algorithm design and analysis Computer bugs Protocols

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