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A programmable built-in self-test for embedded memory cores

IETE Technical Review (Institution of Electronics and Telecommunication Engineers, India) 2007年第4期24卷 287-311页

作者： Banerjee, Shibaji Chowdhury, Dipanwita Roy Bhattacharya, Bhargab B. Department of Computer Science and Engineering Indian Institute of Technology Kharagpur 721 302 India Advanced Computing and Microelectronics Unit Indian Statistical Institute 203 BT Road Kolkata 700 108 India

A memory test algorithm for detecting neighborhood pattern sensitive faults (NPSFs), including static NPSF (SNPSF), passive NPSF (PNPSF) and active NPSF (ANPSF), is proposed in this paper. The patterns can also detect all the traditional faults present in the memory array such as stuck-at faults (SAFs), transition faults (TFs), coupling faults (CFs) and address decoder faults. Next, a programmable BIST architecture is designed. The BIST circuit allows the users to select a vast variety of test algorithms based on their choice. The single BIST circuit is capable of testing different types of memory cores embedded in SOC. The proposed BIST circuit is shared among the different memory cores in an SOC. For this purpose, test wrappers for the shared BIST circuits and the memory cores are designed. Finally, a test scheduling algorithm is developed to reduce the overall test time. Copyright © 2007 by the IETE.

关键词： Built-in self test

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Faster Placer for Island-Style FPGAs

Faster Placer for Island-Style FPGAs

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International Conference on computing: Theory and Applications, ICCTA

作者： Pritha Banerjee Susmita Sur-Kolay Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata India

In this paper, we propose a placement method for island-style FPGAs, based on fast yet very good initial placement followed by refinement using ultra-low temperature simulated annealing. The initial placement is the keystone of the method and the steps to obtain it are: top down coarse partitioning, allocation of partitions to regions on FPGA array, placement of logic blocks within each region and finally the IOs. The solutions thus obtained require 66% fewer moves i.e. about 3x speed-up during final iterative refinement by simulated annealing, whereas the quality of solution is on the average within 2% of optimal. The critical path length obtained after routing does not degrade for the set of 9 benchmark circuits

关键词： Field programmable gate arrays Simulated annealing Routing Switches Costs Computational modeling Logic arrays Circuit simulation Phased arrays Iterative algorithms

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Checkpointing Using Mobile Agents in Distributed Systems

Checkpointing Using Mobile Agents in Distributed Systems

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International Conference on computing: Theory and Applications, ICCTA

作者： Partha Sarathi Mandal Krishnendu Mukhopadhyaya Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata India

Traditional message passing based checkpointing and rollback recovery algorithms perform well for tightly coupled systems. In wide area distributed systems these algorithms may suffer from large overhead due to message passing delay and network traffic. Mobile agents offer an attractive option for designing checkpointing schemes for wide area distributed systems. Network topology is assumed to be arbitrary. Processes are mobile agent enabled. When a process wants to take a checkpoint, it just creates one mobile agent. Concurrent initiations by multiple processes are allowed. Synchronization and creation of a consistent global state (CGS) for checkpointing is managed by the mobile agent(s). In the worst case, for k concurrent initiations among n processes, checkpointing algorithm requires a total of O(kn) hops by all the mobile agents. A mobile agent carries O(n/k) (on the average) size data

关键词： Checkpointing Mobile agents Message passing Network topology Distributed computing Telecommunication traffic System performance Mobile communication Intelligent agent microelectronics

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Distributed Data Gathering Scheduling in Multihop Wireless Sensor Networks for Improved Lifetime

Distributed Data Gathering Scheduling in Multihop Wireless S...

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International Conference on computing (ICCTA 2007): Theory and Applications

作者： Subhasis Bhattacharjee Nabanita Das Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata India

For a multihop sensor network with n sensors, this paper presents an O(n) distributed greedy algorithm for extracting a rooted spanning tree to improve the lifetime of the overall network. It spontaneously determines a data gathering schedule from the sensors towards the base station (the root). No global knowledge about the topology is required for the computation and also each sensor does not need to access the base station directly. Simulation studies show that in terms of system lifetime, the proposed algorithm significantly outperforms the scheduling based on the Minimum Spanning Tree (MST), or the Shortest Path (SP) routing techniques. Performance comparison with PEGASIS [7] shows that the proposed algorithm performs better as more and more nodes die out.

关键词： Spread spectrum communication Wireless sensor networks Processor scheduling Base stations Greedy algorithms Data mining Network topology Computational modeling Scheduling algorithm Routing

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Floorplanning in Modern FPGAs

Floorplanning in Modern FPGAs

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International Conference on VLSI Design

作者： Pritha Banerjee Susmita Sur-Kolay Arijit Bishnu Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata India Department of Computer Science and Engineering Indian Institute of Technology Kharagpur India

ISBN: (纸本)9780769527628;0769527620

State-of-the-art FPGA architectures have millions of gates in CLBs, Block RAMs, and Multiplier blocks which can host fairly large designs. While their physical design calls for floorplanning, the traditional algorithm for ASIC do not suffice. In this paper, we have proposed an algorithm for unified floorplan topology generation and sizing for recent heterogeneous FPGAs. Experimental results on a set of benchmark circuits show that our three step floorplan generation method can produce feasible solutions very fast with 45% improvement in total half perimeter wirelength compared to the very few previous approaches.

关键词： Field programmable gate arrays Application specific integrated circuits Circuit topology Clustering algorithms Simulated annealing microelectronics Computer science Computer architecture Algorithm design and analysis Read-write memory

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Ranking of Optical Character Prototypes in a Large Database Using Isothetic Chord Lengths

Ranking of Optical Character Prototypes in a Large Database ...

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International Conference on computing: Theory and Applications, ICCTA

作者： Partha Bhowmick Arindam Biswas Bhargab B. Bhattacharya Computer Science & Technology Dept Bengal Engineering and Science University Shibpur India Advanced Computing & Microelectronics Unit Indian Statistical Institute Kolkata India

A novel algorithm for conferring a ranking system on the prototypes of a large database of optical/handwritten characters is proposed. The ranking system is designed using the (isothetic) chord lengths of the enclosing isothetic polygons corresponding to the prototypes, for a prescribed grid-size. As the derivation of structural information of a character by thinning or by edge detection is susceptible to its impurity during imaging or post-processing, an isothetic polygon is used that captures the geometric structure of the character in an elegant way. The proposed scheme has a striking potential in deciding the relative merit and usefulness of a particular prototype with respect to the other prototypes of the corresponding character in the concerned database. Several quantitative measures have been suggested, and supporting experimental results have been reported, which justify the strength and efficiency of the proposed method

关键词： Prototypes Spatial databases Optical character recognition software Character recognition Computer science Data engineering Design engineering Optical computing microelectronics Image edge detection

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ICE: The Isothetic Convex Envelope of a Digital Object

ICE: The Isothetic Convex Envelope of a Digital Object

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International Conference on computing: Theory and Applications, ICCTA

A novel algorithm to derive the isothetic convex envelope (ICE) of an object using a digital geometric technique is proposed in this paper. ICE is defined as the isothetic convex polygon that contains the digital object, with an aim of capturing its underlying shape information. Slackening the tightness of an ICE corresponding to a digital object is achievable by increasing the grid size, and for a slackened ICE with lesser output complexity (i.e., with lesser number of vertices), the runtime of the algorithm falls significantly. The proposed algorithm is marked by its dependence on object boundary instead of object size, and usage of primitive integer operations in the digital domain, which, in entirety, ensures its speedy execution and acceptability in a real-world application. Experimental results including CPU time demonstrate the elegance of ICE and the efficiency of the proposed algorithm

关键词： Ice Shape Application software microelectronics Computer science Runtime Computer vision Pattern recognition Algorithm design and analysis Object detection

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computing a planar widest empty α-siphon in o(n3) time

Computing a planar widest empty α-siphon in o(n3) time

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19th Annual Canadian Conference on Computational Geometry, CCCG 2007

作者： Ben-Moshe, Boaz Bhattacharya, Binay K. Das, Sandip Gaur, Daya R. Shi, Qiaosheng Department of Computer Science College of Judea and Samaria 44837 Ariel Israel School of Computing Science Simon Fraser University Burnaby BC V5A 1S6 Canada Advanced Computing and Microelectronics Unit Indian Statistical Institute Calcutta 700 035 India Department of Computer Science University of Lethbridge 4401 University Drive Lethbridge AB T1K 3M4 Canada

Given a set of n points P in the Euclidean plane, we consider the problem of locating a 1-corner polygonal chain X such that minp∈P d(p, X) is maximized. The polygonal chain has the added property that its interior angle is α and it partitions P. In this note we present an algorithm that solves the problem in o(n3) time and space. The previous best running time for this problem was O(n3 log2 n) time [2].

关键词： Chains

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Test pattern generation for power supply droop faults

Test pattern generation for power supply droop faults

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19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design

作者： Mitra, Debasis Bhattacharjee, Subhasis Sur-Kolay, Susmita Bhattacharya, Bhargab B. Zachariah, Sujit T. Kundu, Sandip Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata India Design/Test Technology India Intel Technology India Pvt. Ltd. Bangalore India Dept of ECE University of Massachusetts Amherst United States

ISBN: (纸本)0769525024

In deep sub-micron VLSI chips, when several tran-sistors in physical proximity switch simultaneously, a substantial power supply drop, known as droop, may occur because of concurrent load on a via of the power grid. As a result of lower supply voltage, transistors may slow down. Such timing faults are termed as droop faults. Modeling of droop faults and understanding their effects on the functionality and timing behavior of the circuit are yet to be fully understood. In this paper, a new model for droop faults is proposed. A simple ATPG-based procedure for stuck-at faults has been adapted to test droop faults. For validation of the methodology in combinational circuits, a set of appropriate clusters of gates is selected to cover potential droop-prone regions in a circuit. Experimental results on ISCAS-85 benchmark circuits reveal that a very high droop fault coverage can be obtained by a short sequence of test vectors. © 2006 IEEE.

关键词： VLSI circuits

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Test pattern generation for power supply droop faults

Test pattern generation for power supply droop faults

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International Conference on VLSI Design

作者： D. Mitra S. Bhattacharjee S. Sur-Kolay B.B. Bhattacharya S.T. Zachariah S. Kunduc Advanced Computing & Microelectronics Unit Indian Statistical Institute Kolkata India Design/Test Technology India Intel Technology India Pvt. Ltd. Bangalore India

In deep sub-micron VLSI chips, when several transistors in physical proximity switch simultaneously, a substantial power supply drop, known as droop, may occur because of concurrent load on a via of the power grid. As a result of lower supply voltage, transistors may slow down. Such timing faults are termed as droop faults. Modeling of droop faults and understanding their effects on the functionality and timing behavior of the circuit are yet to be fully understood. In this paper, a new model for droop faults is proposed. A simple ATPG-based procedure for stuck-at faults has been adapted to test droop faults. For validation of the methodology in combinational circuits, a set of appropriate clusters of gates is selected to cover potential droop-prone regions in a circuit. Experimental results on ISCAS-85 benchmark circuits reveal that a very high droop fault coverage can be obtained by a short sequence of test vectors.

关键词： Test pattern generators Power supplies Circuit faults Circuit testing Switches Timing Very large scale integration Power grids Voltage Combinational circuits

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