A 21Mb/mm2 SRAM design using 0.0367um2 HCC bitcell on a 10nm CMOS technology is presented. Gate-modulated self-collapse (GSC) write assist is utilized to enable 175mV reduction in VMIN with minimal energy overhead. In...
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A 21Mb/mm 2 SRAM design using 0.0367um 2 HCC bitcell on a 10nm CMOS technology is presented. Gate-modulated self-collapse (GSC) write assist is utilized to enable 175mV reduction in V MIN with minimal energy overhe...
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ISBN:
(数字)9781728199429
ISBN:
(纸本)9781728199436
A 21Mb/mm 2 SRAM design using 0.0367um 2 HCC bitcell on a 10nm CMOS technology is presented. Gate-modulated self-collapse (GSC) write assist is utilized to enable 175mV reduction in V MIN with minimal energy overhead. Instance area overhead is limited to 3-5% by implementing the GSC circuitry in a row-based configuration with modified SRAM bitcells.
With continuous channel length scaling and ongoing demand for higher operating frequencies, HCI degradation and combining BTI and HCI aging mechanisms in compact aging models becomes important for accurately capturing...
ISBN:
(数字)9781728131993
ISBN:
(纸本)9781728132006
With continuous channel length scaling and ongoing demand for higher operating frequencies, HCI degradation and combining BTI and HCI aging mechanisms in compact aging models becomes important for accurately capturing end-of-life circuit behavior. We have developed an aging playback model that can replay aged transistor I-V characteristics over a large bias range including both mechanisms. The model uses the transistor VT shift, mobility degradation, and a localization coefficient to combine the impact of individual BTI and HCI components. It can be used for both NMOS and PMOS, as well as logic and I/O devices and is part of Intel process design kits.
We discuss advances in our research on 300mm GaN NMOS by demonstrating GaN-on-Si(111) NMOS transistors achieving low R ON =330Ω-μm; high ID,max=1.7mA/μm; BV DS (at I D =1μA/μm) of up to 90V with excellent R ON =...
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ISBN:
(数字)9781728188881
ISBN:
(纸本)9781728188898
We discuss advances in our research on 300mm GaN NMOS by demonstrating GaN-on-Si(111) NMOS transistors achieving low R ON =330Ω-μm; high ID,max=1.7mA/μm; BV DS (at I D =1μA/μm) of up to 90V with excellent R ON =660Ω-μm; record f T /f MAX of 200/350GHz for GaN-on-Si; industry's best RF switch R on C off =55fs; and highest mmwave (28GHz) RF power amplifier peak PAE of 65% @ 19.5dBm saturated power. We discuss and compare the challenges in approaches to GaN and Si CMOS integration research including: (a) poly-silicon CMOS, (b) heterogeneous epitaxy of GaN and Si(111) CMOS, (c) wafer-to-wafer bonding [2], and (d) 3D monolithic Si(100) layer transfer using bonding techniques [1],[3].
Exceptionally low minimum operating voltage (V MIN ) SRAM arrays have been demonstrated on 22nm FinFET low power technology (22FFL) [1]. By optimizing an undoped SRAM transistor and applying industry standard write as...
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Exceptionally low minimum operating voltage (V MIN ) SRAM arrays have been demonstrated on 22nm FinFET low power technology (22FFL) [1]. By optimizing an undoped SRAM transistor and applying industry standard write assist techniques, 16Mb array of 0.087μm 2 high-density bitcell (HDC) and 32Mb array of 0.107μm 2 high-current bitcell (HCC) achieve the 95 th percentile V MIN of 505mV and 450mV respectively across a temperature range of -10°C to 95°C. A self-induced collapse (SIC) write assist integrated into the 6-T HDC SRAM bitcell array enables 110mV V MIN reduction relative to an unassisted array at the 95 th percentile with negligible power overhead.
With continued scaling of CMOS technology, numerous concerns have been raised about random telegraph noise (RTN) possibly matching or exceeding the random process variation in threshold voltage (V th )[1], [2]. These ...
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ISBN:
(纸本)9781509006397
With continued scaling of CMOS technology, numerous concerns have been raised about random telegraph noise (RTN) possibly matching or exceeding the random process variation in threshold voltage (V th )[1], [2]. These studies are usually limited by the small sample size of the measurements, relying on modeling for projecting to high sigma. In this work, we use a modified ring oscillator (RO) circuit to measure the RTN in individual transistors (7500 NMOS and 7500 PMOS), for Intel's current 14nm technology. We analyze this data, carefully characterizing the noise signatures and accounting for the devices not showing RTN. We show that magnitude of V th fluctuation due to RTN (ΔV th RTN ) at the ~3.7 sigma level is th RTN is uncorrelated to V th random variation. From these observations, we conclude that RTN is not a significant limitation for circuit design at Intel's 14nm node.
A 0.094μm2 8T SRAM bitcell is developed for a 14nm technology featuring FinFET transistors with a 70nm contacted gate pitch [1]. The bitcell and supporting circuitry are optimized for high density and aging tolerance...
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A 12b 70MS/s sub-2 radix SAR ADC designed on Intel's 14nm tri-gate CMOS process is presented. It utilizes a startup calibration for correcting capacitor mismatches in its CDAC. The calibration is fully digital and...
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A 0.094μm 2 8T SRAM bitcell is developed for a 14nm technology featuring FinFET transistors with a 70nm contacted gate pitch [1]. The bitcell and supporting circuitry are optimized for high density and aging toleran...
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A 0.094μm 2 8T SRAM bitcell is developed for a 14nm technology featuring FinFET transistors with a 70nm contacted gate pitch [1]. The bitcell and supporting circuitry are optimized for high density and aging tolerance. Supply collapse and wordline boosting techniques are applied for write V MIN assist. A delayed keeper is used for read V MIN improvement. A 400MHz V MIN of 560mV is achieved with the proposed design at -10°C in volume manufacturing.
This work introduces the first high-volume manufacturable metal-fuse technology in a 22nm tri-gate high-k metal-gate CMOS process. A high-density array featuring a 16.4μm2 1T1R bit cell is presented that delivers a r...
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