This work introduces the first high-volume manufacturable metal-fuse technology in a 22nm tri-gate high-k metal-gate CMOS process. A high-density array featuring a 16.4μm 2 1T1R bit cell is presented that delivers a...
详细信息
This work introduces the first high-volume manufacturable metal-fuse technology in a 22nm tri-gate high-k metal-gate CMOS process. A high-density array featuring a 16.4μm 2 1T1R bit cell is presented that delivers a record low program voltage of 1.6V. This low-voltage operability allows the array to be coupled with logic-voltage power delivery circuits. A charge pump voltage doubler operating on a 1V voltage rail is demonstrated in this paper with healthy fusing yield.
This work introduces the first high-volume manufacturable metal-fuse technology in a 22nm tri-gate high-k metal-gate CMOS process. A high-density array featuring a 16.4μm 2 1T1R bit cell is presented that delivers a...
详细信息
This work introduces the first high-volume manufacturable metal-fuse technology in a 22nm tri-gate high-k metal-gate CMOS process. A high-density array featuring a 16.4μm 2 1T1R bit cell is presented that delivers a record low program voltage of 1.6V. This low-voltage operability allows the array to be coupled with logic-voltage power delivery circuits. A charge pump voltage doubler operating on a 1V voltage rail is demonstrated in this paper with healthy fusing yield.
Abstract A discrete-time ΔΣ ADC that utilizes an 8b SAR quantizer with a 4b feedback DAC is presented. The 4 MSBs of the quantizer are fed-back for Δ operation while a digital filter post-processes the full 8b and ...
详细信息
A discrete-time ΔΣ ADC that utilizes an 8b SAR quantizer with a 4b feedback DAC is presented. The 4 MSBs of the quantizer are fed-back for Δ operation while a digital filter post-processes the full 8b and improves ...
详细信息
ISBN:
(纸本)9781467355315
A discrete-time ΔΣ ADC that utilizes an 8b SAR quantizer with a 4b feedback DAC is presented. The 4 MSBs of the quantizer are fed-back for Δ operation while a digital filter post-processes the full 8b and improves the resolution. The ΔΣ modulator has a single stage 2nd order feed-forward topology with Fs=240MHz and OSR=8. The ADC achieves 66dB SNDR, 15MHz bandwidth, and consumes 12.7mW power. This ADC is designed in Intel's tri-gate 22nm CMOS process.
Increasing process variation in advancedtechnology nodes requires sustained process and circuit innovation to meet yield, performance and margin requirements for SRAM memories. Memory assist circuits are becoming an ...
详细信息
Increasing process variation in advancedtechnology nodes requires sustained process and circuit innovation to meet yield, performance and margin requirements for SRAM memories. Memory assist circuits are becoming an important tool in co-developing critical scaled memory solutions and can have significant impact on process optimization, as well as power consumption, minimum operating voltage and performance of memories.
A novel transient voltage collapse (TVC) technique is presented to enable low-voltage operation in SRAM. By dynamically switching off the PMOS during write operations with a collapsed supply voltage below the data ret...
详细信息
A novel transient voltage collapse (TVC) technique is presented to enable low-voltage operation in SRAM. By dynamically switching off the PMOS during write operations with a collapsed supply voltage below the data retention voltage, a minimum operating voltage (V ccmin ) of 0.6V is demonstrated in a 32nm 12-Mb low-power (LP) SRAM. Data retention failure of unselected cells is mitigated by controlling the duration of voltage collapse. Circuit-process co-optimization is critical to ensure robust circuit design margin of TVC technique.
This paper describes the advantages of the thin gate oxide transistors with negative word-line (WL) architecture implemented in the embedded DRAM macro. The macros with the negative WL architecture are fabricated as w...
详细信息
This paper describes the advantages of the thin gate oxide transistors with negative word-line (WL) architecture implemented in the embedded DRAM macro. The macros with the negative WL architecture are fabricated as well as the macros with the conventional WL architecture. We found the retention time of the negative WL architecture is longer by more than 5 times than that of the conventional WL architecture.
暂无评论