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New structure transistors for advanced technology node CMOS ICs

National Science review 2024年第3期11卷 24-41页

作者： Qingzhu Zhang Yongkui Zhang Yanna Luo Huaxiang Yin Integrated Circuit Advanced Process R&D Center Institute of Microelectronics of Chinese Academy of Sciences(IMECAS) State key Lab of Fabrication Technologies for Integrated Circuits Institute of Microelectronics of Chinese Academy of Sciences School of Integrated Circuits University of Chinese Academy of Sciences

Over recent decades, advancements in complementary metal-oxide-semiconductor integrated circuits(ICs)have mainly relied on structural innovations in transistors. From planar transistors to the fin field-effect transistor(FinFET) and gate-all-around FET(GAAFET), more gate electrodes have been added to three-dimensional(3d) channels with enhanced control and carrier conductance to provide higher electrostatic integrity and higher operating currents within the same device footprint. Beyond the 1-nm node, Moore's law scaling is no longer expected to be applicable to geometrical shrinkage. Vertical transistor stacking, e.g. in complementary FETs(CFET), 3d stack(3dS) FETs and vertical-channel transistors(VFET), for enhanced density and variable circuit or system design represents a revolutionary scaling approach for sustained IC development. Herein, innovative works on specific structures, key process breakthroughs, shrinking cell sizes and design methodologies for transistor structure research and development are reviewed. Perspectives on future innovations in advanced transistors with new channel materials and operating theories are also discussed.

关键词： transistor CMOS GAAFET CFET 3dS FET

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Microstructural Evolution Near Microcrack in AZ31 Mg Alloy Under Electropulses

Microstructural Evolution Near Microcrack in AZ31 Mg Alloy U...

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Magnesium Technology Symposium held at the TMS Annual Meeting and Exhibition, 2024

作者： Yu, Jinyeong Lee, Seong Ho Cheon, Seho Mun, Mooseong Lee, Jeong Hun Lee, Taekyung School of Mechanical Engineering Pusan National University Busan46241 Korea Republic of Advanced Forming Process R&D Group Korea Institute of Industrial Technology Ulsan44413 Korea Republic of

ISBN: (纸本)9783031502392

Electropulsing treatment (EPT) is a novel method utilizing the Joule effect for efficient metal heating. EPT's advantages over traditional furnace methods have led to growing interest, particularly its defect-repair potential at sub-melting temperatures. Our study introduces an alternative EPT process using direct current (dC) for reduced energy consumption and enhanced scalability. The research involves applying square wave pulses with varying current densities to AZ31 magnesiumMagnesium, examining microstructural changes in pre-cracked sheets under EPT. Subsequent fatigueFatigue tests induce controlled pre-cracks, revealing localized welding around the cracks post-EPT. The study diverges by proposing a "current detour effect" and a point-wise current source amplifying the Joule effect for defect repairdefect repair. Observed {10−12} extension twins support the hypothesis, attributed to the compressive stress from EPT. However, calculated thermal compressive stress remains below the CrSS for the {10−12} twin. distinct recrystallizationrecrystallization kinetics, such as continuous static recrystallization, might be influential around the entire crack regions. © The Minerals, Metals & Materials Society 2024.

关键词： Compressive stress

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Effects of the VGS sweep range on the short channel effect in negative capacitance FinFETs

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Science China(Information Sciences) 2024年第6期67卷 463-464页

作者： Fan ZHANG Zhaohao ZHANG Jiaxin YAO Qingzhu ZHANG Gaobo XU Zhenhua WU Huan LIU Genquan HAN Yan LIU Huaxiang YIN Integrated Circuit Advanced Process R&D Center State Key Lab of Fabrication Technologies for Integrated CircuitsInstitute of Microelectronics of Chinese Academy of Sciences School of Microelectronics Xidian University School of Integrated Circuits University of Chinese Academy of Sciences

As the CMOS technology scaling is reaching fundamental limits,there is a substantial demand for energy-efficient devices with lower operating *** capacitance field-effect transistors （NCFETs） exhibit the capability to amplify the gate voltage and become promising candidates for future advanced process *** （FE） HfO2-based materials,

关键词： channel sweep range capacitance effects finfets negative short

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Fano resonance from Air-mode Photonic Crystal Nanobeam Cavity with 248-nm dUV Lithography

Fano Resonance from Air-mode Photonic Crystal Nanobeam Cavit...

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2023 Opto-Electronics and Communications Conference, OECC 2023

作者： Sun, Fujun Yang, Gang Zhang, Peng Tang, Bo Li, Zhihua Li, Bin Yang, Yan Institute of Microelectronics Integrated Circuit Advanced Process R&D Center of IMECAS Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781665462136

Photonic crystal nanobeam cavity (PCNC) is important building block for large-scale photonic integrated circuits (PICs). Nevertheless, most state-of-the-art demonstrations rely on electron beam lithography (EBL). Here, we experimentally present the characteristics of Fano resonance from air-mode PCNC using 248-nm deep ultraviolet (dUV) lithography for the first time. Experimentally high average Q factor of ∼ 1.58 × 104 is achieved. © 2023 IEEE.

关键词： Electron beam lithography

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Nanosheet Count Optimization Strategy of Complementary FET (CFET) Scaling beyond 2 nm from device to Circuit 7

Nanosheet Count Optimization Strategy of Complementary FET (...

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7th International Workshop on advanced Patterning Solutions, IWAPS 2023

作者： He, Hao Li, Shixin Luo, Yanna Xu, Haoqing Yin, Huaxiang Wu, Zhenhua EDA Center Institute of Microelectronics Beijing China Integrated Circuit Advanced Process R&D Center Institute of Microelectronics Beijing China

ISBN: (纸本)9798350344547

Complementary Field-Effect Transistors is one of the most promising structures for replacing GAA (Gate-All-Around) field-effect transistors while continuing the advancement of Moore's Law. Thus, optimizing its structure is a crucial research direction. This study proposes a nano-sheet count design strategy to address the issue of mismatched electron and hole mobilities in standard CFET cell and a nine-stage ring oscillator (rO). The simulation results demonstrate the effective matching of electron and hole mobilities by adjusting the ratio of NMOS (n-type) and PMOS (p-type) nano-sheet counts, thus enabling the optimization of circuit performance and power consumption for specific applications. In the CFET of the rO unit, a frequency increase of 10% and a capacitance reduction of 6% are achieved with only a 3% increase in power consumption, comparing a CFET with four P-doped nano-sheet channels and two N -doped nano-sheet channels to one with three P-doped nano-sheet channels and three N-doped nano-sheet channels. © 2023 IEEE.

关键词： Field effect transistors

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Analysis of Indium-Silver Alloy Thermal Interface Material reliability and Coverage degradation Mechanisms 26

Analysis of Indium-Silver Alloy Thermal Interface Material R...

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26th Electronics Packaging Technology Conference, EPTC 2024

作者： Kong, MinJae Park, dongHyeon ree, Won Koo, YoungJun Bae, JoHyun Jeong, YeonKi Sohn, EunSook ryu, dongSu Park, dongJoo Park, Kyungrok Advanced Process & Material Project Global R&D center Amkor Technology Korea Inc. 150 Songdomirae-ro Yeonsu-gu Incheon21991 Korea Republic of

ISBN: (纸本)9798331522001

Thermal management of microprocessor chips has emerged as a critical issue to ensure high-power operation, especially in high-performance computing (HPC) applications such as artificial intelligence (AI). To effectively transfer the heat generated from the chip junction to the heat spreader or heat sink, the development of thermal interface materials (TIMs) with high thermal conductivity and the processes for applying them are very active in the electronics packaging industry. In general, polymer-based TIMs have been widely developed and used for their mechanical properties and process workability. However, due to the limitations of polymers, the thermal conductivity required for HPC applications cannot be satisfied. Indium (In) has been widely selected for high power consumption devices as a high dielectric constant (k) TIM due to its high thermal conductivity. However, the low liquidus point of In can be problematic for flip chip lidded ball grid array (FCLBGA) applications since indium may be re-melted during ball attachment reflow, which can reduce TIM coverage [3]. In this paper, indium-silver (InAg)-based alloys were evaluated to develop high thermal conductivity TIM solutions that can be applied to large body FCBGA devices and examines the reliability of indium-silver alloy TIMs under thermal cycling conditions. By varying the silver content, we investigated its impact on mechanical stability and TIM coverage degradation. Indium alloy with higher silver content showed reduced package warpage and fewer voids, as observed through Shadow moiré and SAT inspection. In contrast, Indium alloys with lower silver content exhibited more significant structural deformation and void formation Our findings suggest that increasing silver content in indium alloys enhances the TIM coverage and mechanical stability with better thermal performance. © 2024 IEEE.

关键词： Indium alloys

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domain Adaptation based Fin Height Measurement for drAM 5

Domain Adaptation based Fin Height Measurement for DRAM

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5th IEEE International Women in Technology Conference, WINTECHCON 2024

作者： Singh, ramya Bagavath Sultania, Gaurav Pedapudi, Lakshmi Narayana Ahn, Joonyoung Song, Je Ung Ahn, Hyomin Smart Equipment Solutions Group Samsung Semiconductor India Research Bangalore India Advanced Process Development Team 4 Semiconductor R&D Center Hwaseong Korea Republic of

ISBN: (纸本)9798350374070

Fin Height is critical quality parameter of drAM device and its measurement is destructive process. This measurement process has some disadvantages – destroying wafer/chips, limitation on number of chips for measurement leads to less data samples, and its availability towards end of production cycle. Ability of system to predict fin height early/mid production cycle serves vital role to reduce redundancy and save losses in the production pipeline. With the advent of Spectroscopic methods like Ellipsometry (SE), reflectometry, Interferometry, it is possible to capture spectral characteristics of devices in non-destructive framework. ML/dL modelling of spectrum data learns fin height characteristics and aids prediction. Simulation of drAM for spectrum data enables more learning data, helps to enhance fin height prediction by not just data augmentation technique of simulated data to real data. We adopt and employ domain Adaptation (dA) methods for regression problem where dA mostly dealt with classification problem. We demonstrate significant improvement in fin height prediction accuracy by using simulated data in addition to real data via various domain Adaptation methods. © 2024 IEEE.

关键词： dynamic random access storage

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design and Simulation of Hinge-type ro-ro (roll-on/roll-off) Ship Car deck Structure 33rd

Design and Simulation of Hinge-type Ro-Ro (Roll-on/Roll-off)...

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33rd International Ocean and Polar Engineering Conference, ISOPE 2023

作者： Kim, Hyun Soo Cho, Min Goo Kang, Sung Wook Kim, Jae Woong Pyo, Chang Min Ji, Chang Wook Park, Jang Ik Precision Mechanical Process and Control R&D Group Korea Institute of Industrial Technology Gyeongsangnam-do Jinju Korea Republic of Automotive Materials & Components R&D Group Korea Institute of Industrial Technology Gwangju Korea Republic of Advanced Forming Process R&D Group Korea Institute of Industrial Technology Ulsan Korea Republic of Research center Dae Lyun Engineering Co. Ltd. Busan Korea Republic of

ISBN: (纸本)9781880653807

ro-ro ships can roll-on or roll-off cargo with self-driving power such as passenger cars and trucks, and container cargo on transport devices such as trucks or trailers on a ramp. The representative types of ro-ro ships are PCC (Pure Car Carrier) and PTCT (Pure Car & Truck Carrier). ro-ro ship is configured to load as many cargoes as possible by dividing the cargo hold into multiple card decks up and down. It is necessary to adjust the height of the car deck according to the type of vehicle being loaded. For this purpose, a number of fillers are installed on the inner deck of the ro-ro ship. In other words, to load high cargo such as heavy equipment on the car deck, the height between the decks must be high. At this time, the liftable car deck is adjusted using the deck lifter installed on the pillar. Existing liftable car deck structures are made of a single large plate, so it takes a lot of time and money to install and dismantle them. In this study, a hinge-type liftable car deck was designed. In addition, the overall structural integrity including the hinge was evaluated through structural analysis in accordance with the classification regulations. © 2023 by the International Society of Offshore and Polar Engineers (ISOPE).

关键词： Arctic engineering

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Improve the Breakdown Voltage of Silicon Pixel Sensor With Optimized Multi-Guard rings

Improve the Breakdown Voltage of Silicon Pixel Sensor With O...

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2023 China Semiconductor Technology International Conference, CSTIC 2023

作者： Sun, Peng Xu, Gaobo Fu, Jianyu ding, Mingzheng Yan, Yinan Zhang, Luoyun Yin, Huaxiang Institute of Microelectronics Chinese Academy of Sciences Integrated Circuit Advanced Process R&d Center Beijing100029 China University of Chinese Academy of Sciences Beijing100049 China

ISBN: (纸本)9798350311006

The silicon pixel sensor (SPS) for X-ray free electron laser detection requires ultra-high operating voltage. In this paper, for an optimized multi-guard rings, a SPS with ultra-high breakdown voltage and low leakage is obtained. The effect of the arrangement of the multi-guard rings on the SPS breakdown is investigated by TCAd simulation. It is found that SPS with a gradually increasing gap from inner ring to outer ring has a higher breakdown voltage. Guided by this, the multi-guard ring structure of SPS is optimized and applied into the manufacture of devices. Finally, the optimized SPS exhibits an ultra-high breakdown voltage of exceeding 1,800 V;and the dark current of per pixel is approximately 2.0 pA at a bias voltage of 1,000 V. © 2023 IEEE.

关键词： Electric breakdown

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The advanced Failure Analysis methods based on dynamic Hot Electron Analyzer and Idd3P Measurements for HKMG Sub-nm drAM 50

The Advanced Failure Analysis methods based on Dynamic Hot E...

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50th International Symposium for Testing and Failure Analysis Conference, ISTFA 2024

作者： Lee, Sunah Son, Jihoon Park, Jihoon Jeon, Bohyeon Yun, Seokmin Kim, Chaesoo Kwon, Hagyeong Lee, Jayoung Kim, Sangjun Jung, Ilwoo Park, SeGuen DRAM Process Architecture Team Samsung Electronics Gyeong-gi-do Hwasung-si Korea Republic of Advanced Analysis Science & Engineering Team Semiconductor R&D Center Samsung Electronics Gyeong-gi-do Hwasung-si Korea Republic of

ISBN: (纸本)9781627084918

In this paper, we propose an advanced failure analysis method for specifying the location of gate-related fails in the High-k Metal Gate (HKMG) MOSFET. The test sample for this experiment is the sub-15nm technology drAM (dynamic random Access Memory) which consists of high speed HKMG transistors. In terms of HKMG transistors, the modification of gate materials and process schemes provoke the various gate related failures in drAM which makes it more difficult to examine the sample with conventional analyzing methods. So, Idd3P measurement methods along with dynamic Hot Electron Analyzer (HEA) were employed as an advanced fault localization method. Idd3P measurement data provides word-line (WL) dependent failure types which distinguishes the gate-related failures from other irrelevant failures. [1] From the dynamic HEA with the MAGNUM tester, the accurate failure sites can be obtained. Newly combined two analytical methods that we present in this paper are effective in localizing the failure sites more accurate than previously suggested methods. © 2024 ASM International®

关键词： dynamic random access storage

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