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Short-Channel Performance and Mobility Analysis of <110>- and <100>-Oriented Tri-Gate Nanowire MOSFETs with raised Source/drain Extensions

Short-Channel Performance and Mobility Analysis of <110>- an...

引用

Symposium on VLSI Technology

作者： M. Saitoh Y. Nakabayashi H. Itokawa M. Murano I. Mizushima K. Uchida T. Numata Advanced LSI Technology Laboratory Corporate R&D Center 8 Shinsugita-cho Isogo-ku Yokohama 235-8522 Japan Process & Manufacturing Engineering Center SemiconductorCompany Toshiba Corporation 8 Shinsugita-cho Isogo-ku Yokohama 235-8522 Japan Tokyo Institute of Technology 8 Shinsugita-cho Isogo-ku Yokohama 235-8522 Japan

ISBN: (纸本)9781424454518

Nanowire transistors (NW Tr.) are promising for ultimate scaling [1]. However, parasitic resistance (rsd) [2,3] and NW mobility (p) degradation [4] limit 4. Although Schottky S/d was proposed for low rn, [2], silicidation- process of NW is hard to control [5]. Also, quantitative understanding of NW mobility is still insufficient. Moreover, most studies reported <110> NW Tr. and short-L performance of <100> NW Tr. has not been examined yet.

关键词： Mobility Analysis MOSFETs raised Source

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Vertical cell array using TCAT(Terabit Cell Array Transistor) technology for ultra high density NANd flash memory

Vertical cell array using TCAT(Terabit Cell Array Transistor...

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Symposium on VLSI Technology

作者： Jaehoon Jang Han-Soo Kim Wonseok Cho Hoosung Cho Jinho Kim Sun Il Shim Younggoan Jae-Hun Jeong Byoung-Keun Son dong Woo Kim Kihyun Jae-Joo Shim Jin Soo Lim Kyoung-Hoon Kim Su Youn Yi Ju-Young Lim dewill Chung Hui-Chang Moon Sungmin Hwang Jong-Wook Lee Yong-Hoon Son U-In Chung Won-Seong Lee Samsung Electronics Co. Ltd Giheung-Gu Yongin-City Gyeonggi-Do Korea Memory Research and Development Center Memory Division Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Advanced Technology Development Team 2&Process Development Team Memory R&D Center

Vertical NANd flash memory cell array by TCAT (terabit cell array transistor) technology is proposed. damascened metal gate SONOS type cell in the vertical NANd flash string is realized by a unique dasiagate replacementpsila process. Also, conventional bulk erase operation of the cell is successfully demonstrated. All advantages of TCAT flash is achieved without any sacrifice of bit cost scalability.

关键词： SONOS devices Plugs Costs Etching Transistors Scalability Nonhomogeneous media dielectric substrates Sun Moon

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Three-dimensional Stress Engineering in FinFETs for Mobility/On-Current Enhancement and Gate Current reduction

Three-Dimensional Stress Engineering in FinFETs for Mobility...

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Symposium on VLSI Technology

作者： Masumi Saitoh Akio Kaneko Kimitoshi Okano Tomoko Kinoshita Satoshi Inaba Yoshiaki Toyoshima Ken Uchida Advanced LSI Technology Laboratory Corporate R&D Center Process & Manufacturing Center Yokohama 235-8522 Japan

ISBN: (纸本)9781424418022

In this paper, the first systematic study of uniaxial stress effects on mobility (μ)/on-current (I{sub}(on)) enhancement and gate current (I{sub}g) reduction in FinFETs is described. We demonstrate for the first time that I{sub}g of (110) side-surface pFinFETs is largely reduced by longitudinal compressive stress due to out-of-plane mass increase. (110) n/pFinFETs are superior to (100) FinFETs in terms of higher μ/I{sub}(on) enhancement ratio by longitudinal strain and comparable/higher short-channel I{sub}(dsat). Three-dimensional stress design in FinFETs including transverse and vertical stresses is proposed based on the understanding of stress effects beyond bulk piezoresistance.

关键词： Fin field effect transistors Stress effects three dimensional stress gate current compressive stresses longitudinal strain refractive surgery enhancement Transverse

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2-stack 1d-1r Cross-point Structure with Oxide diodes as Switch Elements for High density resistance rAM Applications

2-stack 1D-1R Cross-point Structure with Oxide Diodes as Swi...

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2007 IEEE International Electron devices Meeting (IEdM 2007), vol.2

作者： Myoung-Jae Lee Youngsoo Park Bo-Soo Kang Seung-Eon Ahn Changbum Lee Kihwan Kim Wenxu. Xianyu G. Stefanovich Jung-Hyun Lee Seok-Jae Chung Yeon-Hee Kim Chang-Soo Lee Jong-Bong Park In-Gyu Baek In-Kyeong Yoo Samsung Advanced Institute of Technology Semiconductor Device Laboratory Gyeonggi-Do Korea Nano Fabrication Technology Center Samsung Advanced Institute of Technology Gyeonggi-Do Korea Analytical Engineering Center Samsuna Advanced Institute of Technology Gyeonggi-Do Korea Advanced Process Development Team Semiconductor R&D Center Gyeonggi-Do Korea

We have successfully integrated a 2-stack 8×8 array 1d-1r (one diode-one resistor) structure with 0.5μm×0.5μm cells in order to demonstrate the feasibility of high density stacked rrAM. p-CuO{sub}X/n-InZnO{sub}X heterojunction thin film was used for the first time as a oxide diode which shows increased current density of two orders over our previous p-NiO{sub}x/n-TiO{sub}x oxide diode. And Ti-doped NiO was used for the storage node. No limitation to the number of stacks has been observed from our results. Cell and device properties of our cross-point structure 8×8 array are reported. In addition, all fabrication processes were done at room temperature without other dedicated facilities or processes allowing for compatibility with current CMOS technology. Bi-stable switching for 1d-1r memory was demonstrated for our 2-stack cross-point structures showing excellent behavior for both diode and storage nodes. The forward current density for p-CuO{sub}X/n-IZO{sub}X diodes was over 10{sup}4 A/cm{sup}2, and the operation voltage for the storage node with diode attached was around 3V.

关键词： Switches diodes Current density CMOS technology read-write memory resistors Heterojunctions Transistors Fabrication Temperature

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Fabrication of a direct-type silicon pixel detector for a large area hybrid x-ray imaging device

Fabrication of a direct-type silicon pixel detector for a la...

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IEEE Symposium on Nuclear Science (NSS/MIC)

作者： Kun-Sik Park Tae-Woo Kim Yong-Sun Yoon Jong-Moon Park Jin-Yeong Kang Jin-Gun Koo Bo-Woo Kim J. Kosonen Kwang-Soo No Electronics and Telecommunications Research Institute Semiconductor Process Team Daejeon South Korea Department of Materials Science and Engineering Korea Advanced Institute of Science and Technology Daejeon South Korea X-ray Sensor R&D Center Value Added Technologies Company Limited Hwaseong South Korea

We demonstrated the design and the fabrication processes of a direct-type silicon pixel detector for a digital dental radiography made using a high-resistive n-type silicon substrate. The structure of the detector is based on a fully-depleted p-i-n diode. The detector is composed of 644,328 pixels with a pitch of 35 mum. The size of the detector is 2.58 cm x 3.47 cm and it is composed of a 4-block assembly with four read-out CMOS ICs. We focused on experimentally evaluating the process conditions for the silicon pixel detector to reduce the leakage current and improve the breakdown voltage. From the experimental results, we found that the high temperature drive-in after p + ion implantation deteriorates the leakage current and p + passivation by thermal oxidation improves the breakdown voltage. The leakage current of a pixel was 0.07 pA/pixel and the breakdown voltage was more than 1700 V. The read-out IC consists of a current-integrating pixel readout CMOS chip and PbSn bumps. After bump-bonding four read-out ICs to a pixel detector and wire-bonding to a PCB, X-ray image tests showed a resolution of 11 lp/mm and provided a good image of human teeth.

关键词： Fabrication Silicon Pixel X-ray detection X-ray detectors X-ray imaging Leakage current dentistry radiography P-i-n diodes

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Novel Heat dissipating Cell Scheme for Improving a reset distribution in a 512M Phase-change random Access Memory (PrAM)

Novel Heat Dissipating Cell Scheme for Improving a Reset Dis...

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Symposium on VLSI Technology

作者： d.H. Kang J.S. Kim Y.r. Kim Y.T. Kim M.K. Lee Y.J. Jun J.H. Park F. Yeung C.W. Jeong J. Yu J.H. Kong d.W. Ha S.A. Song J. Park Y.H. Park Y.J. Song C.Y. Eum K.C. ryoo J.M. Shin d.W. Lim S.S. Park J.H. Kim W.I. Park K.r. Sim J.H. Cheong J.H. Oh J.I. Kim Y.T. Oh K.W. Lee S.P. Koh S.H. Eun N.B. Kim G.H. Koh G.T. Jeong H.S. Jeong Kinam Kim Advanced Technology Development Team 2 Yongin-City Gyunggi-Do South Korea Semi. Business Samsung Electronic Co. Ltd. Yongin-City Gyunggi-Do South Korea CAE Yongin-City Gyunggi-Do South Korea Analytical Engineering Center Samsung Advanced Institute of Technology Yongin-City Gyunggi-Do South Korea Process Analysis & Control Group Memory R&D Div. Yongin-City Gyunggi-Do South Korea

ISBN: (纸本)4900784036;97

Programming with larger current than optimized one is often preferable to ensure a good resistance distribution of high-resistive reset state in high-density phase-change random access memories because it is very effective to increase the resistance of cells to a target value. In this paper, we firstly report that this larger current writing may conversely degrade the reset distribution by reducing the resistance of normal cells via the partial crystallization of amorphous Ge 2 Sb 2 Te 5 and this degradation can be suppressed by designing a novel cell structure with a heat dissipating layer.

关键词： Phase change random access memory Crystallization degradation Amorphous materials Writing resistance heating Temperature Phase change materials Switches Cooling

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Study on High Performance (110) PFETs with Embedded SiGe

Study on High Performance (110) PFETs with Embedded SiGe

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International Electron devices Meeting (IEdM)

作者： S. Okamoto K. Miyashita N. Yasutake T. Okada H. Itokawa I. Mizushima A. Azuma H. Yoshimura T. Nakayama System LSI Division Toshiba Corporation Yokohama Japan Advanced LSI Technology Laboratory Corporate R&D Center Toshiba Corporation 8 Shinsugita-cho Isogo-ku Yokohama 235-8522 Japan Phone: +81-45-776-5758 Fax: +81-45-776-4111 Process and Manufacturing Engineering Center Semiconductor Company Toshiba Corporation 8 Shinsugita-cho Isogo-ku Yokohama 235-8522 Japan Phone: +81-45-776-5758 Fax: +81-45-776-4111 Center For Semiconductor R&D Semiconductor Company Toshiba Corporation 8 Shinsugita-cho Isogo-ku Yokohama 235-8522 Japan Phone: +81-45-776-5758 Fax: +81-45-776-4111

The effects of inversion-layer capacitance and stress-induced mobility at short channel region (L g =35 nm) on (100) and (110) pFETs are investigated. 64 % mobility enhancement at E eff = 1.1 MV/cm and 0.15 nm thinner inversion-layer capacitance at E ox = 4.5 MV/cm are obtained for (110) embedded SiGe (eSiGe) pFETs, compared to (100) eSiGe pFETs. Calculated results suggest that (110) eSiGe pFETs will gain additional 63% higher mobility with 1 GPa uniaxial stress by controlling surface roughness scattering at SiO 2 /Si(110) interface.

关键词： Silicon germanium Germanium silicon alloys Capacitance Stress Scattering Boron Large scale integration research and development rough surfaces Surface roughness

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Highly Manufacturable Single Metal Gate process Using Ultra-Thin Metal Inserted Poly-Si Stack (UT-MIPS)

Highly Manufacturable Single Metal Gate Process Using Ultra-...

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International Electron devices Meeting (IEdM)

作者： Sung Kee Han Hyung-Suk Jung Hajin Lim Min Joo Kim Cheol-kyu Lee Mong sub Lee Young-sub You Hion Suck Baik Young Su Chung Eunha Lee Jong-Ho Lee Nae In Lee Ho-Kyu Kang Advanced Process Development Team System LSI Division Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Semiconductor R&D Center Memory Division Samsung Electronics Company Limited South Korea AE Center Samsung Advanced Institute of Technology Gyeonggi South Korea

The authors have successfully developed a mass production friendly single metal gate process utilizing an ultra-thin metal inserted poly-Si stack (UT-MIPS) structure. First, the inserted metal gate thickness effects on device performances are carefully examined, and then the other parameters are optimized to give the best performance. As a results, low and symmetrical short channel Vth (0.44/-0.48 V for n/pMOS) and excellent drive currents (620/230 muA/mum for n/pMOS at Ioff =20pA/mum and Vdd=1.2 V) are obtained without using any mobility enhancement strain technology. The estimated operation voltage for 10 years lifetime of optimized UT-MIPS devices (1.25 V for nMOS PBTI and 1.5 V pMOS NBTI) are well beyond the 1.2 V, showing the good reliability characteristics of UT-MIPS devices as well

关键词： Manufacturing processes Mass production Optimized production technology dielectrics Large scale integration research and development Capacitive sensors Life estimation Lifetime estimation Voltage

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PBTI & HCI characteristics for high-k gate dielectrics with poly-Si & MIPS (metal inserted poly-Si stack) gates

PBTI & HCI characteristics for high-k gate dielectrics with ...

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Annual International Symposium on reliability Physics

作者： Hyung-Suk Jung Sung Kee Han Min Joo Kim Jong Pyo Kim Yun-Seok Kim Ha Jin Lim Seok Joo doh Jung Hyoung Lee Mi Young Yu Jong-Ho Lee Nae-In Lee Ho-Kyu Kang Seong Geon Park Sang Bom Kang Advanced Process Development Project Samsung Electronics Co. Ltd. Yongin-City Kyunggi-Do Korea Process Development Team 2 Semiconductor Research & Development Center Samsung Electronics Company Limited South Korea Process Development Team 2 Semiconductor R&D Center

ISBN: (纸本)0780388038

reliability characteristics of high-k gate dielectrics with poly-Si gates and metal inserted poly-Si stack (MIPS) gates are investigated in terms of positive bias temperature instability (PBTI) and hot carrier injection (HCI) characteristics. The results indicate that the dopants (P or As) from the poly-Si severely degrade PBTI and HCI characteristics. Therefore, the high-k/MIPS structure, which is not influenced by gate dopants, shows significant improvement in PBTI and HCI characteristics. For the same reason, the worst HCI condition of high-k/poly-Si structure is V/sub g/=V/sub d/ instead of V/sub g/ at I/sub sub/spl ***/max/, while that of high-k/MIPS structure is V/sub g/ at I/sub sub/spl ***/max/.

关键词： Human computer interaction degradation MOSFET circuits Boron High K dielectric materials High-K gate dielectrics CMOS process CMOS technology Electrodes Large scale integration

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Multi-layer cross-point binary oxide resistive memory (OxrrAM) for post-NANd storage application

Multi-layer cross-point binary oxide resistive memory (OxRRA...

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International Electron devices Meeting (IEdM)

作者： I.G. Baek d.C. Kim M.J. Lee H.-J. Kim E.K. Yim M.S. Lee J.E. Lee S.E. Ahn S. Seo J.H. Lee J.C. Park Y.K. Cha S.O. Park H.S. Kim I.K. Yoo U. Chung J.T. Moon B.I. ryu Process Development Team Samsung Electronics Co. Ltd. Yongin si South Korea Process Development Team Semiconductor R&D Center Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Devices Lab. Samsung Advanced Institute of Technology Yongin-City Kyeonggi-Do Korea Process Development Team Samsung Electronics Co. Ltd.

Feasibility of the multi-layer cross-point structured binary oxide resistive memory (OxrrAM) has been tested for next generation non-volatile random access high density data storage application. Novel plug contact type bottom electrode (plug-BE) could reduce active memory cell diameter down to 50nm with smaller operation current and improved switching distributions. With 2 additional masks, one layer of plug-BE included cross-point memory array could be added on top of another one. No signal of inter-layer interference has been observed. Also, prototype binary oxide based diodes have been fabricated for the purpose of suppressing intra-layer interference of cross-point memory array

关键词： Electrodes Testing Memory Plugs Energy consumption CMOS technology Moon research and development Consumer electronics Electronic mail

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