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2023 China Semiconductor Technology International Conference, CSTIC 2023

作者： Yao, Jiaxin Zhang, Xuexiang Cao, Lei Li, Junjie Zhou, Na Li, Qingkun Wei, Yanzhao Luo, Yanna Luo, Jun Zhang, Qingzhu Yin, Huaxiang Institute of Microelectronics of Chinese Academy of Sciences Integrated Circuit Advanced Process R&d Center Beijing100029 China Institute of Microelectronics of Chinese Academy of Sciences Key Laboratory of Microelectronics Devices and Integrated Technology Beijing100029 China University of Chinese Academy of Sciences Beijing100049 China

ISBN: (纸本)9798350311006

In this work, the significant leakage reduction approach is proposed and investigated by critical spacer bottom footing (SBF) optimization for gate-all-around (GAA) stacked Si nanosheet (SiNS) transistors. The fabricated GAA stacked SiNS CMOS transistors and standard 6T static random-access memory (SrAM) cell have achieved reduced static-state leakage current by an order of magnitude and improved read static noise margin (rSNM) by +12.67% due to SBF optimization. The performance boosting origins from improving the gate and source/drain overlap doping profile via SBF optimization, and thus suppressing the band to band tunneling leakage current correspondingly. The proposed leakage reduction approach can inspire and broaden the ultralow power performance application for the state-of-the-art GAA nanosheet technology. © 2023 IEEE.

关键词： CMOS integrated circuits

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domain Adaptation Based fin Height Measurement for drAM

Domain Adaptation Based fin Height Measurement for DRAM

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Women in Technology Conference (WINTECHCON), 2022 IEEE

作者： ramya Bagavath Singh Gaurav Sultania Lakshmi Narayana Pedapudi Joonyoung Ahn Je Ung Song Hyomin Ahn Smart Equipment Solutions Group Samsung Semiconductor India Research Bangalore India Advanced Process Development Team 4 Semiconductor R&D Center Hwaseong South Korea

ISBN: (数字)9798350374070

ISBN: (纸本)9798350374087

Fin Height is critical quality parameter of drAM device and its measurement is destructive process. This measurement process has some disadvantages - destroying wafer/chips, limitation on number of chips for measurement leads to less data samples, and its availability towards end of production cycle. Ability of system to predict fin height early/mid production cycle serves vital role to reduce redundancy and save losses in the production pipeline. With the advent of Spectroscopic methods like Ellipsometry (SE), reflectometry, Interferometry, it is possible to capture spectral characteristics of devices in non-destructive framework. ML/dL modelling of spectrum data learns fin height characteristics and aids prediction. Simulation of drAM for spectrum data enables more learning data, helps to enhance fin height prediction by not just data augmentation technique of simulated data to real data. We adopt and employ domain Adaptation (dA) methods for regression problem where dA mostly dealt with classification problem. We demonstrate significant improvement in fin height prediction accuracy by using simulated data in addition to real data via various domain Adaptation methods.

关键词： Semiconductor device measurement Pipelines random access memory Termination of employment Production reflectometry Predictive models Height measurement Transistors Interferometry

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Material Extrusion for Ceramic Additive Manufacturing with Polymer-Free Ceramic Precursor Binder

SSRN

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SSrN 2022年

作者： Hur, Hyuk Park, Yu Jin Kim, dong-Hyun Ko, Jong Wan 3D Printing Manufacturing Process Center Advanced Forming Process R&D Group Korea Institute of Industrial Technology Techno saneop-ro 29beon-gil Ulsan44776 Korea Republic of

Additive manufacturing of dense ceramic products has been challenging because of the high polymeric content of the feedstock materials. Several studies have been conducted to increase the ceramic content in the feedstock, but the binder and additives in it have remained in the polymeric content. A novel strategy for highly dense additive manufacturing using a sol-gel-based ceramic slurry without polymeric additives is presented. Alumina, which is the most widely used fine ceramic, was chosen as a representative ceramic material. The proposed sol-gel solution enabled a high solid loading of approximately 50 vol. % without any polymeric dispersant while satisfying the requirements of material extrusion, such as extrudable viscosity ( © 2022, The Authors. All rights reserved.

关键词： Aluminum oxide

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Optimal design of WET Etching Bath for 3d Flash Memories Using Multi-Objective Bayesian Optimization

Optimal Design of WET Etching Bath for 3D Flash Memories Usi...

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Joint e-Manufacturing and design Collaboration Symposium (eMdC) & International Symposium on Semiconductor Manufacturing (ISSM)

作者： Miyuki Kouda Yumi Mori Tomohiko Sugita Youyang Ng AI & System Research Center Frontier Technology R&D Institute KIOXIA Corporation Yokkaichi-shi Japan AI & System Research Center Frontier Technology R&D Institute KIOXIA Corporation Yokohama-shi Japan Advanced Memory Process Development Center Memory Division KIOXIA Corporation Yokkaichi-shi Japan

ISBN: (数字)9798331510589

ISBN: (纸本)9798331510596

In recent years, the complexity of semiconductor manufacturing processes has increased, leading to a growing need for the high-precision optimization of device structures. For example, in batch-type wet etching devices, the flow of chemical liquids within the process bath can vary depending on the device structure, causing variations in the etching state of the wafer. This issue is addressed using a feedback mechanism that iteratively adjusts the device structure based on the results of an etching experiment, thereby achieving more uniform etching conditions. However, this approach requires a large number of trial experiments. In the fabrication process of 3d flash memories, word-line formation in the silicon substrate requires precise control of the silicon concentration in the etching solution. However, this concentration can fluctuate due to the dissolution of the SiN film during the etching process. This fluctuation may cause various problems. This study introduces an innovative method utilizing multi-objective Bayesian optimization to derive optimal wet etching bath design parameters; this method is informed by image and physical-quantity data from fluid dynamics simulations [1]. This approach is validated through simulation experiments, whose results are used to identify the best possible wet etching bath designs effectively.

关键词： Wet etching Three-dimensional displays Fluid dynamics Semiconductor device manufacture Silicon Bayes methods Flash memories Optimization Silicon dioxide Substrates

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Experimental Investigation of Ultra-Low Temperature LA2O3/HFO2Bi-Layer dipole-First process Using PVd Method for advanced IC Technology

Experimental Investigation of Ultra-Low Temperature LA2O3/HF...

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2023 China Semiconductor Technology International Conference, CSTIC 2023

作者： Wei, Yanzhao Yao, Jiaxin Xu, renren Zhang, Qingzhu Yin, Huaxiang Chinese Academy of Sciences Integrated Circuit Advanced Process R&d Center Institute of Microelectronics Beijing100029 China Institute of Microelectronics Chinese Academy of Sciences Key Laboratory of Microelectronic Devices and Integrated Technology Beijing100029 China University of Chinese Academy of Sciences School of Integrated Circuits Beijing100049 China

ISBN: (纸本)9798350311006

In this paper, a La2O3/HfO2 bi-layer dipole-first (dF) process is proposed and investigated by ultra-low temperature PVd dielectric laminates to achieve lower gate effective work function (EWF) for monolithic 3d-IC (M3d) application. The impacts of ultra-low temperature La-dipole on EWF modulation and interfacial properties are comprehensively investigated. It is found that the flat-band voltage (VFB) negatively shifts 60 mV with sub-1nm La2O3 thickness, which provides an effective way to meet the require of Si conduction band-edge EWF modulation. Furthermore, the electron trap/detrap densities (Not) and interfacial trap densities (dit) are suppressed by La2O3/HfO2 bi-layer dF process to improve device performance. These results exhibit a promising bi-layer dF process in low thermal integration for advanced IC technology. © 2023 IEEE.

关键词： Timing circuits

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Improve the Breakdown Voltage of Silicon Pixel Sensor With Optimized Multi-Guard rings

Improve the Breakdown Voltage of Silicon Pixel Sensor With O...

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China Semiconductor Technology International Conference (CSTIC)

作者： Peng Sun Gaobo Xu Jianyu Fu Mingzheng ding Yinan Yan Luoyun Zhang Huaxiang Yin Integrated Circuit Advanced Process R&D Center Institute of Microelectronics Chinese Academy of Sciences Beijing China University of Chinese Academy of Sciences Beijing China

The silicon pixel sensor (SPS) for X-ray free electron laser detection requires ultra-high operating voltage. In this paper, for an optimized multi-guard rings, a SPS with ultra-high breakdown voltage and low leakage is obtained. The effect of the arrangement of the multi-guard rings on the SPS breakdown is investigated by TCAd simulation. It is found that SPS with a gradually increasing gap from inner ring to outer ring has a higher breakdown voltage. Guided by this, the multi-guard ring structure of SPS is optimized and applied into the manufacture of devices. Finally, the optimized SPS exhibits an ultra-high breakdown voltage of exceeding 1,800 V; and the dark current of per pixel is approximately 2.0 pA at a bias voltage of 1,000 V.

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Improvement of Line roughness of Fin by Conventional Thermal Oxidation and Atomic Level Low-Temperature Ozone Treatments

Improvement of Line Roughness of Fin by Conventional Thermal...

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China Semiconductor Technology International Conference (CSTIC)

作者： Peng Wang Guanqiao Sang Yihong Lu Wenjuan Xiong renjie Jiang Lei Cao QingKun Li Lianlian Li Jiaxin Yao Yadong Zhang Meihe Zhang Qingzhu Zhang Junfeng Li Huaxiang Yin Jun Luo Academy of Sciences Integrated Circuit Advanced Process R&D Center Institute of Microelectronics of the Chinese Beijing China University of Chinese Academy of Sciences Beijing China ChangChun University of Science and Technology Changchun China

ISBN: (数字)9798350362190

ISBN: (纸本)9798350362206

In this paper, conventional thermal oxidation (CTO) and atomic level low-temperature ozone (LTO) treatment were utilized to successfully thin the width of fin and reduce the surface roughness. Meanwhile, the line edge roughness (LEr) and line width roughness (LWr) of fin were compared under the two schemes. The result show that after three sacrificial oxidizations and dHF rinsing, the LEr and LWr of fins were reduced by 40.1% (from 4.64 nm to 2.78 nm) and 55.5% (from 2.38 nm to 1.06 nm), respectively. In addition, after 12 cycles of LTO and HF rinsing, the LEr and LWr of fin decreased by 67.4% (from 4.30 nm to 1.40 nm) and 61.3% (from 2.66 nm to 1.03 nm), respectively. And, the cross-correlation coefficients (ρ) were 0.92 and 0.72, respectively. The result provide a guidance for channel surface optimization and low-temperature integration of FinFET devices at advanced technology nodes.

关键词： Integrated circuits Gases Hafnium dH-HEMTs FinFETs Oxidation Surface roughness

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Performance Enhancement and Mechanism Analysis of IGZO Thin-Film Transistors Utilizing Interdigital Structure

Performance Enhancement and Mechanism Analysis of IGZO Thin-...

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17th Symposium on Thin Film Transistors, TFT 2024, held at the PriME 2024 Meeting

作者： Lu, Yupeng Yan, Gangping Yang, Yanyu Sun, Peng Luo, Jie Bao, Yunjiao Niu, Chuqiao Wang, Peng Xu, Gaobo Wang, Guilei Chao, Zhao Yin, Huaxiang Luo, Jun School of Integrated Circuits University of Chinese Academy of Sciences Beijing100049 China State Key Lab of Fabrication Technologies for Integrated Circuits Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China Integrated Circuit Advanced Process R&D Center Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China Beijing Superstring Academy of Memory Technology China

ISBN: (纸本)9781623326630

—This study investigates the issue of leakage current reduction in oxide semiconductor thin-film transistors (TFTs) with interdigital structures. Electrical measurements clearly demonstrate that the leakage current of interdigitated IGZO devices decreases as the on/off ratio increases. To explore the reasons behind the reduction in leakage current, we conducted two-dimensional device simulations. The results confirm that the use of interdigital structures can influence the electric field distribution within the device channel, introducing shielding electric fields. As the number of interlayer structures between the source and drain increases, the shielding electric fields proportionally increase. Additionally, interdigitated IGZO devices exhibit a large on/off ratio exceeding 2.7×1010, an ultra-low leakage current of less than 3×10-16 A/μm, and a high saturation mobility of 9.4 cm2/Vs. These findings provide valuable insights for designing low-power, high-performance devices based on IGZO. ©The Electrochemical Society.

关键词： Thin film transistors

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Hybrid simulation method of quantum characteristics for advanced Si MOSFETs under extreme conditions by incorporating simplified master equation with TCAd

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results in Physics 2024年 63卷

作者： Zhu, Xiaohui Yin, Huaxiang Integrated Circuit Advanced Process R&D Center and State Key Lab of Fabrication Technologies for Integrated Circuits Institute of Microelectronics of the Chinese Academy of Sciences University of Chinese Academy of Sciences

Silicon (Si)-based quantum-dot (Qd) device by advanced CMOS process is one of important technologies for quantum computing application and currently, it needs a fast and accurate quantum characteristics simulation for designing and optimizing the devices. In this paper, for the first time, a fast hybrid simulation method is proposed by incorporating simplified quantum master equation model with the traditional TCAd tool. Additionally, a SPICE MOdEL is incorporated for transient current correction to achieve results closer to real observations. The Qd devices forming on advanced stacked Si nanowire (NW) and stacked Si nanosheet (NS) are constructed and simulated by this method, yielding Coulomb diamond plot and charge energies for different structures at 1 K. Notably, a Coulomb blockade region of approximately 82 mV and a first Coulomb step width approximately 1.6 times wider than the blockade region are observed, consistent with theoretical expectations and confirming the method's efficacy. Simulation characteristics of advanced diamond-like channel devices are obtained within 1277 s, demonstrating over 85% matching with experimental data. Meanwhile, the influence of quantum characteristics varying with the transistor's structure and process parameters is also analyzed, which in turn provide a guidance for the design and the optimization of the Qd device by advanced Si CMOS process. © 2024

关键词： Hybrid simulation Master equation Quantum dots TCAd

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development of an Fe-Based Alloy with reinforced Austenite and Packet Lath Martensite as Filler Metals for 9% Ni Steel

SSRN

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SSrN 2022年

作者： Choi, Kwangsu Hwang, Jiyong Jung, Hyo Yun Advanced Forming Process R&D Center Korea Institute of Industrial Technology Ulsan44413 Korea Republic of Department of Materials Science and Metallurgical Engineering Kyungpook National University Daegu41566 Korea Republic of

Typically, 9% Ni steel is welded with Ni-based filler metal composed of expensive elements, such as Ni and Mo . In this study, a novel Fe-based alloy composed of inexpensive elements was designed for the welding of 9% Ni steel. The gas tungsten arc welding process with superior electric current stability was selected to evaluate the weldability and welding properties. The weld metal produced during single- and multi-passed welding formed the microstructure, which comprised equiaxed packet lath martensite and prior austenite. The suitability of the mechanical properties of the proposed Fe-based filler metal for 9% Ni steel welding was verified via tensile tests of the weld joint and base metal, namely the 9% Ni steel, at 25 ℃ and −163 ℃. In comparison with the 9% Ni steel, the Fe-based filler metal improved the yield and tensile strengths of weld joints by more than 5.5% at room and cryogenic temperatures. Additionally, the tensile fracture of the specimen occurred in the base metal and not in the weld metal or the heat-affected zone, confirming the high stiffness of the weld metal. Therefore, the proposed Fe-based filler metal can serve as an economical material for welding the 9% Ni steel. © 2022, The Authors. All rights reserved.

关键词： Filler metals

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