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Micro touch sensor array made by hydrothermal method

Micro touch sensor array made by hydrothermal method

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International Symposium on Micromechatronics and Human Science (MHS)

作者： G. Kwon F. Arai T. Fukuda K. Itoigawa Y. Tsukahara Department of Micro System Engineering Nagoya University Japan Center for Cooperative Research in Advanced Science and Technology Nagoya University R&D DIV. R&D Center Tokai Rika Co.LTD. Japan

We propose a micro touch sensor array, which can be used in high temperature environments. The PZT thin film was made on a Ti substrate by the hydrothermal method, and the electrodes were deposited on its surfaces to form the sensor and the actuator. The actuator part is driven at a resonance frequency of 1.045 kHz and the actuating voltage is 5V. The sensing part can detect the impedance change before and after the contact. The sensor structure is simple and easy to miniaturize and it works below high temperatures (under 82/spl deg/C). This sensor can be used as the control touch sensor pad of a car instead of the conventional capacitive type touch pad, because it can resist high temperatures. The paper reports the basic properties of the sensor.

关键词： Sensor arrays Tactile sensors Temperature sensors Thin film sensors Actuators Sputtering Substrates Electrodes resonance resonant frequency

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A reconfigurable multilevel parallel graphics cache memory with 75 GB/s parallel cache replacement bandwidth

A reconfigurable multilevel parallel graphics cache memory w...

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Symposium on VLSI Circuits

作者： Se-Jeong Park Jeong-Su Kim ramchan Woo Se-Joong Lee Kang-Min Lee Tae-Hum Yang Jin-Yong Jung Hoi-Jun Yoo Department of Electrical Engineering Korea Advanced Institute of Science and Technology Daejeon South Korea Memory R&D Division HYUNDAI Electronics Advanced Circuit Design Team Incheon South Korea

ISBN: (纸本)4891140143

A dedicated single-chip multilevel parallel graphics cache memory for high-speed parallel texture mapping in PC graphics has been fabricated by a 0.16 /spl mu/m drAM technology. The proposed cache architecture is composed of four components: 1) an 8 MB drAM L2 cache, 2) eight 16 KB SrAM L1 parallel caches, 3) eight pipelined texture data filters, 4) serial-to-parallel latches. The refill bandwidth of the parallel L1 cache is maximized up to 75 GB/sec by a hidden double data transfer scheme between the L2 and L1 caches. Furthermore, by adaptive sub-wordline activation scheme, the line sizes of the L2 and L1 caches are reconfigurable for achieving optimal cache miss rate and lower power consumption. The SrAM L1 caches and the texture filters by use of parallel pipelined structures result in higher system performance.

关键词： Graphics Cache memory random access memory Bandwidth Filters Layout Energy consumption System performance Surface texture Pipelines

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Effect of ground guard fence with via and ground slot on radiated emission in multi-layer digital printed circuit board

Effect of ground guard fence with via and ground slot on rad...

引用

IEEE International Symposium on Electromagnetic Compatibility (EMC)

作者： H. Lee Jonghoon Kimi Seungyoung Ahn Jung-Gun Byun deog-Soo Kang Cheol-Seung Choi Hae-Jin Hwang Joungho Kim Department of Electrical Engineering and Computer Science Korea Advanced Institute of Science and Technology Kusong Taejon Korea Korea Advanced Institute of Science and Technology Daejeon Daejeon KR System R&D Group Digital Media Business Samsung Electronics Co. Ltd. Suwon Korea

In high-speed digital printed circuit board (PCB), the ground guard fence is often used to reduce the radiated emission and the crosstalk. Moreover, it is quite useful for the presence of the ground slot under the signal trace to avoid the reflection and the radiated emission. In this paper, the effects of the guard fence are studied by experimental measurement and numerical electromagnetic simulation. It is found that the ground guard fence acts efficiently as the shielding wall against the signal trace, which results in the significant reduction of the radiated emission. Also, its inherent low radiation property works well at presence of the ground slot under the signal trace.

关键词： Microstrip Printed circuits Circuit testing digital printing Electromagnetic radiation Electromagnetic shielding Numerical simulation digital circuits dielectric substrates research and development

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Study on coined solder bumps on micro-via PCBs

Study on coined solder bumps on micro-via PCBs

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International Symposium on Electronic Materials and Packaging

作者： Jae-Woong Nah K.W. Paik Won-Hoe Kim Ki-rok Hur Department of Materials Sci. & Engineering Korea Advanced Institute of Science and Technology Daejeon South Korea Circuit R&D Center Samsung Electro Mechanics Company Limited Yeongi Gun Chungcheongnam South Korea Bump 2 Team Microscale Company Limited Pyeongtaek Gyeonggi South Korea

ISBN: (纸本)0780371577

In this study, three solders, Sn-37Pb, Sn-3.5Ag, and Sn3.8-Ag-0.7Cu, were screen printed on both electroless Ni/Au and OSP finished micro-via PCBs. The pad opening size and pitch of micro-via PCB were 120 /spl mu/m and 230 /spl mu/m respectively. The diameter of the screen printed solder bumps was 150 /spl mu/m and the height above the solder mask was 85 /spl mu/m. After that, the solder bumps were coined until 25 /spl mu/m in height by a newly developed coining machine with variable pressure, temperature, and time. The Sn-37Pb solder formed less amounts of intermetallic compounds than all other Pb-free solders on both electroless Ni/Au and OSP (organic solderability preservatives) finished PCBs during solder reflows because of the lower Sn content and lower reflow temperature. For OSP finish, fracture occurred 100% within the solder regardless of reflow numbers. However, for Ni/Au finish, a brittle fracture at the Ni-Sn IMC layer or the interface between the Ni-Sn intermetallic and the P-rich layer was observed after several reflows. The relation of coining load vs. height of coined solder bump showed three stages of coining deformation. Coining loads needed for same height deformation increased as applied coining rate increased. And the planarity of coined solder bump could be increased as the coining rate decreased. As the coining temperature increased, lower coining loads were needed.

关键词： Flip chip Temperature Costs Assembly Printing Surface finishing Gold Intermetallic Packaging Materials science and technology

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Non-data-aided timing recovery algorithm for /spl pi//4-QPSK modulated signals

Non-data-aided timing recovery algorithm for /spl pi//4-QPSK...

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IEEE International Conference on Communications (ICC)

作者： Beomsup Kim Jun Mo Koo Joonsuk Lee Byung Jun Min Seung Hee Choi Department of EECS Korea Advanced Institute of Science and Technology Taejon South Korea R&D Center SK Telecom Sungnam Kyunggi South Korea

A new baseband clock recovery algorithm for /spl pi//4-QPSK modulated signals is presented. Conventional data-aided algorithm for /spl pi//4-QPSK modulated signals achieves good jitter performance, but suffers from slow initial acquisition and are prone to the potential error accumulation. Several non-data-aided timing recovery algorithms showing jitter performance approaching that of data-aided ones are proposed. rayleigh fading and Gaussian noise are considered in the simulation. Simulation results show that the proposed non-data-aided algorithms satisfy the necessary requirements under rayleigh fading.

关键词： rectifiers Phase locked loops Clocks Constellation diagram Phase modulation Band pass filters Timing jitter Quadrature phase shift keying Pulse modulation Signal generators

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development and evaluation of a digital radiographic system based on CMOS image sensor

Development and evaluation of a digital radiographic system ...

引用

IEEE Symposium on Nuclear Science (NSS/MIC)

作者： H.K. Kim G. Cho S.W. Lee Y.H. Shin H.S. Cho Department of Nuclear Engineering Korea Advanced Institute of Science and Technology Daejeon South Korea R&D Center Korea Advanced Institute of Science and Technology Daejeon South Korea Department of Medical Engineering Yonsei University Wonju South Korea

A cost-effective digital radiographic system with a large field-of-view (FOV) of 17"/spl times/17" has been developed. The cascaded imaging system mainly consists of 3 parts: (1) a phosphor screen to convert incident X-rays into visible photons, (2) an 8/spl times/8 array matrix lens assembly to efficiently collect visible photons emitted by the phosphor screen; and (3) 8/spl times/8 complementary metal-oxide-semiconductor (CMOS) image sensors, aligned to the corresponding lens assembly. Although low in cost due to economical CMOS image sensors, the overall performance features are comparable with other commercial digital radiographic systems. From the analysis of signal and noise propagation, the system is not an "X-ray quantum-limited" system, rather the system has a secondary quantum sink at the light collecting stage. The system resolution is about 2 line-pairs per millimeter from both of the measurement from X-ray images of a line-pair test pattern and the calculation of the modulation-transfer function. detailed experimental and theoretical analysis of performance is discussed.

关键词： radiography Phosphors X-rays Optoelectronic and photonic sensors Sensor arrays Lenses Assembly systems CMOS image sensors Optical imaging Image converters

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A 7.1 GB/s low-power 3d rendering engine in 2d array-embedded memory logic CMOS

A 7.1 GB/s low-power 3D rendering engine in 2D array-embedde...

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IEEE International Conference on Solid-State Circuits (ISSCC)

作者： Yong-Ha Park Seon-Ho Han Jung-Su Kim Se-Joong Lee Jeong-Hun Kook Jae-Won Lim ramchan Woo Hoi-Jun Yoo Jeong-Hwan Lee Jay-Hyun Lee Department of Electrical Engineering Korea Advanced Institute of Science and Technology Taejon South Korea System IC R&D Laboratory Hyundai Electronics Industries Company Limited Kyoungki South Korea

Embedded memory logic (EML) is already studied for a possible solution to the system on a chip. Several different architectures are reported for maximal utilization of memory bandwidth between processor and memory. The one-dimensional processor and memory array has been applied to image processing or 2d graphics. Two-dimensional array architecture, however, is well matched to 3d graphic rendering application because basic primitives of 3d graphics such as triangles or rectangles have 2-dimensional spatial locality on the screen and they can be concurrently processed using a 2-dimensional array architecture. This 3d graphic rendering engine based on the 2d array embedded memory logic has 8 edge processors (EP), 64 pixel processors (PP), 64 frame buffers (FB) and 64 serial access memories (SAM) on the same chip. Its 3d operations include the Gouraud shading, alpha blending, depth comparison and double buffering.

关键词： Logic arrays Engines CMOS logic circuits Interpolation Graphics random access memory Bandwidth rendering (computer graphics) CMOS technology research and development

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Bayesian bootstrap filtering for the LEO satellite orbit determination

Bayesian bootstrap filtering for the LEO satellite orbit det...

引用

IEEE Conference on Vehicular technology (VTC)

作者： Soohong Kim Joohwan Chun R&D I Group LG Precision Company Limited Yongin si Kyunggi South Korea Department of Electrical Engineering Korea Advanced Institute of Science and Technology Taejon South Korea

This paper presents a new Bayesian bootstrap filtering approach for the low Earth orbit (LEO) satellite orbit determination using magnetometer measurements. To overcome the divergence problem of the extended Kalman filter (EKF), a hybrid bootstrap filter is proposed. The filters uses the magnitude of the magnetic field vector as measurements, and does not need the attitude information of the satellite. According to our simulation study our algorithm converges rapidly to the arc orbital parameters even in the presence of large initial position errors, and attains a few tens of kilometers of the position estimation error.

关键词： Bayesian methods Filtering Low earth orbit satellites Extraterrestrial measurements Magnetic field measurement Filters Magnetometers Magnetic sensors Magnetic separation Switches

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A 3d X-ray microtomographic system with CMOS image sensor

A 3D X-ray microtomographic system with CMOS image sensor

引用

IEEE Symposium on Nuclear Science (NSS/MIC)

作者： S.W. Lee H.K. Kim G. Cho Y.H. Shin Y.Y. Won Department of Nuclear Engineering Korea Advanced Institute of Science and Technology Daejeon South Korea R&D Center Star V-Ray TBI Korea Advanced Institute of Science and Technology Daejeon South Korea Department of Orthopedic Surgery School of Medicine Ajou University Suwon South Korea

High resolution and three dimensional X-ray imaging is becoming more and more popular nowadays. An X-ray microtomographic system with CMOS image sensor has been developed. We have developed a novel area X-ray detector with cost-effective CMOS image sensor. The sensing area of the detector is 55 mm/spl times/55 mm and the light from the phosphor screen is collected to the CMOS image sensor by a carefully designed optical system. 6 lenses are assembled to reduce the radiation damage effect and increase the resolution and sensitivity. Microfocus X-ray tube which can reach up to 5 /spl mu/m of focal spot size and microprecision motor system which can move in x-y-z direction for both alignment and magnification and rotate the,object have been adopted. Conventional 3d cone-beam Feldkamp reconstruction algorithm was used and a human cancellous bone has been imaged with this system. Currently, the resolution of this system is about 40 /spl mu/m but the application in microtomography seems very promising using this CMOS X-ray detector.

关键词： X-ray imaging CMOS image sensors Image resolution X-ray detectors radiation detectors Phosphors Optical design Optical sensors Lenses Assembly systems

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The solder joint and runner metal reliability of wafer-level CSP (Omega-CSP)

The solder joint and runner metal reliability of wafer-level...

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Electronic Components and technology Conference (ECTC)

作者： In-Soo Kang Jong-Heon Kim I.S. Park Ki-rok Hur Soon-Jin Cho Hun Han Jin Yu Module PKG Team Memory R&D Division Hyundai Electronics Industries Company Limited Incheon South Korea Department of Materials Science &Engineering Korea Advanced Institute of Science and Technology Taejon South Korea

Wafer-level Chip Size Package (Wafer Level CSP)s are competing with normal CSPs because they provide the benefits of real chip size package with low manufacturing cost. However, solder joint and runner metal reliability in board level are still critical to the acceptance of WLCSP as an alternative package. In Hyundai Electronics, Wafer-Level CSP without underfill, called Omega-CSP, has been developed for a high speed drAM application. Omega CSP has a newly developed dielectric polymer as a stress buffer and modified redistribution process. This work aimed at the assessment of the solder joint reliability characteristics and the runner metal reliability. We studied and examined the reliability in terms of the property of dielectric polymer and the runner structure. According to the results, it was found that solder joint reliability strongly depended on the solder ball size and runner thickness. In addition, the effects of CTE/modulus of dielectric polymer on the reliability solder joint will be discussed.

关键词： Soldering Chip scale packaging Electronics packaging Wafer scale integration dielectrics Polymers Manufacturing Costs random access memory Stress

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