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检索条件"机构=Advanced Lithography Process Technology Department Device Process Development Center"

共 37 条记录，以下是11-20 订阅

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Design intent application to tolerance-based manufacturing system

Design intent application to tolerance-based manufacturing s...

引用

作者： Kobayashi, Sachiko Tanaka, Satoshi Kyoh, Suigen Maeda, Shimon Kajiwara, Masanari Inoue, Soichi Nakamae, Koji Toshiba Corporation Advanced Lithography Process Technology Department Device Process Development Center 8 Shinsugita-cho Isogo-ku Yokohama City Kanagawa-Pref 235-8522 Japan Osaka University Graduate School of Information Science and Technology 2-1 Yamada-oka Suita-shi Osaka Japan

Continuous shrinkage of the design rule in large-scale integrated circuit devices brings about greater difficulty in the manufacturing process. The keys to meeting small process margin are adequate extraction of critical dimension tolerance for each object, considering design intent in terms of electrical behavior, and assigning the tolerance for each process step. However, once the design data are converted to layout data and signed off, most of the design intent is abandoned and unrecognized in the process phase. Thus, uniform and redundant tolerance is used, and therefore, excess tolerance is assigned for some layouts. To solve the problem described above, a tolerance-based manufacturing system utilizing flexible layout-dependent speculation derived from design intent has been discussed. Using a 40-nm node test chip, electrically critical spots, such as timing, cross-talk noise, electromigration, with small margins are extracted, assigned to the physical layout, and utilized in the manufacturing process. The flow is applicable for optical proximity effect correction (OPC) turnaround time reduction, optimization of OPClithography compliance check (LCC) specification, and failure-analysis acceleration. Consequently, a design-intent-aware manufacturing system is promising for realizing proper process specifications and computational cost reduction, in addition to yield enhancement. © 2011 Society of Photo-Optical Instrumentation Engineers (SPIE).

关键词： Specifications

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Extremely small 40 GBPS optical interconnection sub-assembly using GI 50/125 thin plastic optical fibers

Extremely small 40 GBPS optical interconnection sub-assembly...

引用

20th International Conference on Plastic Optical Fibers, POF 2011

作者： Nishigaki, M. Schlepple, N. Obara, K. Uemura, H. Furuyama, H. Sugizaki, Y. Shibata, H. Advanced BEOL Technology Department Device Process Development Center Corporate Research and Development Center/Toshiba Corporation 8 Shinsugita-Cho Isogo-Ku Yokohama 235-8522 Japan

An extremely small optical interconnection sub-assembly, which carries large-capacity signal transmissions of 40 Gbps and fits in the connector plug of an active optical cable, has been developed. The optical sub-assembly (OSA) fabricated by easy steps and solely passive alignment is composed of an ultracompact optoelectronic (OE) ferrule and four thin graded-index plastic optical fibers. The active optical cable using the OSA is a promising application for digital consumer electronics such as 4k2k high definition video.

关键词： Plastic optical fibers

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Design intent utilization for lithography compliance check and layout refinement to improve manufacturability

Design intent utilization for lithography compliance check a...

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IEEE International Symposium on Semiconductor Manufacturing

作者： Sachiko Kobayashi Atsuhiko Ikeuchi Kazunari Kimura Toshiya Kotani Satoshi Tanaka Suigen Kyoh Shimon Maeda Soichi Inoue Advanced Lithography Process Technology Department Device Process Development Center Corporate Research & Development Center Toshiba Corporation Japan Design Methodology Development Group Design Technology Development Department Analog & Imaging Ic Division Toshiba Corporation Semiconductor Company Japan

A collection of slides from the authors conference presentation about the design intent utilization for lithography compliance check and layout refinement to improve manufacturability is presented.

关键词： lithography Timing Data mining Loss measurement Wires Design methodology

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A 6Gbps 3mW optical receiver with DCOC-combined ATC in 65nm CMOS

A 6Gbps 3mW optical receiver with DCOC-combined ATC in 65nm ...

引用

37th European Solid-State Circuits Conference, ESSCIRC 2011

作者： Akita, Ippei Tsubouchi, Yuta Itakura, Tetsuro Nishigaki, Michihiko Uemura, Hiroshi Furuyama, Hideto Shibata, Hideki Corporate Research and Development Center Toshiba Corporation Kawasaki 212-8582 Japan Device Process Development Center Toshiba Corporation Yokohama 235-8522 Japan Department of Electrical and Electronic Information Engineering Toyohashi University of Technology Toyohashi Japan

ISBN: (纸本)9781457707018

This paper presents a 0.48-mW/Gbps optical receiver in a 65-nm CMOS process. The receiver includes a tran-simpedance amplifier (TIA) with a DC offset canceler (DCOC) combined with an autothreshold controller (ATC) function for providing low-power, area-efficient single-ended-to-differential conversion. The fabricated 6-Gbps optical receiver consumes 2.86-mW power and achieves less than -3.8-dBm sensitivity at a BER of 10-11. © 2011 IEEE.

关键词： CMOS integrated circuits

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Novel VTH self-adjusting MISFET with SiN charge trap layer for ultra low power LSI

Novel VTH self-adjusting MISFET with SiN charge trap layer f...

引用

International Electron devices Meeting (IEDM)

作者： Kosuke Tatsumura Atsushi Kawasumi Shigeru Kawanaka Advanced LSI Technology Laboratory Corporate Research and Development Center Toshiba Corporation Yokohama Japan Wireless & Analog Design Department Center of Semiconductor Research and Development Semiconductor & Storage Products Company Toshiba Corporation Yokohama Japan Advanced CMOS Technology Department Device Process Development Center Corporate Research and Development Center Toshiba Corporation Yokohama Japan

A novel V TH self-adjusting FET with SiN charge trap layer is proposed and experimentally demonstrated. The V TH self-adjusting FET has a poly Si/SiN/SiO 2 /Si gate stack and can be introduced to conventional CMOS platform with a small additional cost. The |V TH | of the V TH self-adjusting nFET and pFET decrease on on-state and come back to the initial high value on off-state due to charging and neutralization of the SiN layer by exchange of electrons with gate electrode. The dynamic V TH tuning ability improves both of read and write margins of SRAM. V TH tuning ability of 100mV is achieved by Si-rich SiN film of less than 1nm, which leads to reduction of minimum operating voltage (V DD_min ) of SRAM by 170mV. It is found that switching energy efficiency (energy per a cycle) can be improved largely beyond the limit of conventional FET in ultra low V DD region by V TH self-adjusting function.

关键词： Silicon compounds FETs Logic gates Electron traps Silicon CMOS integrated circuits Switches

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A 6Gbps 3mW optical receiver with DCOC-combined ATC in 65nm CMOS

A 6Gbps 3mW optical receiver with DCOC-combined ATC in 65nm ...

引用

European Conference on Solid-State Circuits (ESSCIRC)

作者： Ippei Akita Yuta Tsubouchi Tetsuro Itakura Michihiko Nishigaki Hiroshi Uemura Hideto Furuyama Hideki Shibata Department of Electrical and Electronic Information Engineering Toyohashi University of Technology Toyohashi Japan Corporate Research & Development Center Toshiba Corporation Kawasaki Japan Device Process Development Center Toshiba Corporation Yokohama Japan

关键词： Optical receivers CMOS integrated circuits Optical buffering Optical variables measurement Optical sensors Bit error rate

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Contribution of carbon to growth of strained silicon, dopant activation and diffusion in silicon

Contribution of carbon to growth of strained silicon, dopant...

引用

10th International Workshop on Junction technology, IWJT-2010

作者： Itokawa, Hiroshi Advanced Unit Process Technology Department Device Process Development Center Corporate Research and Development Center Toshiba Corporation 8 Shinsugita-Cho Isogo-Ku Yokohama 235-8522 Japan

ISBN: (纸本)9781424458691

C incorporation into Si and SiGe has become essential in modern high-performance CMOSFET technology. The reason is that C atom is markedly useful in growing strained Si film and controlling diffusion of dopant atoms in Si and SiGe layers. In this paper, contribution of C atoms to the growth of strained Si and SiGe films, the activation and the diffusion of B in Si are described. Interstitial C atoms inhibit an epitaxial growth of strained Si:C and SiGe films in both case for the C implantation followed by annealing and for the epitaxial growth of SiGe:C by RP-CVD. Suppressions of the localized change in strain caused by C incorporation and the localized C atoms successfully achieve a high-crystallinity strained Si:C and SiGe:C films with a high substitutional concentration. A B activation ratio in Si varies depending on incorporated C concentration in the wide range of C and B concentration. Furthermore, C atoms enhance the growth of stable B-containing clusters at a high B concentration region in Si, resulting in decrease in the B activation ratio in Si layer. © 2010 IEEE.

关键词： Si-Ge alloys

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Carbon incorporation into substitutional silicon site by carbon cryo ion implantation and metastable recrystallization annealing as stress technique in n-metal-oxide-semiconductor field-effect transistor

Carbon incorporation into substitutional silicon site by car...

引用

10th International Workshop on Junction technology, IWJT-2010

作者： Itokawa, Hiroshi Miyano, Kiyotaka Oshiki, Yusuke Onoda, Hiroyuki Nishigoori, Masahito Mizushima, Ichiro Suguro, Kyoichi Advanced Unit Process Technology Department Device Process Development Center Corporate Research and Development Center Japan System LSI Division Semiconductor Company Toshiba Corporation 8 Shinsugita-cho Isogo-ku Yokohama 235-8522 Japan

ISBN: (纸本)9781424458691

Since the lattice constant of silicon-carbon (Si:C) is smaller than that of Si, Si:C embedded in the source and drain (e-Si:C S/D) can induce tensile stress in the channel and improve the electron mobility of n-metal-oxide- semiconductor field-effect transistors (nMOSFETs). In this research, C ion cryo implantation and a metastable recrystallization schemes employed to achieve strained Si:C layers with a high substitutionally incorporated carbon concentration ([C]sub) at a high ratio of substitution, and a high doping activation were studied. we proposed the C cryo implantation for reduced implantation damage, the fast recrystallization by nonmelt laser annealing combined with solid phase epitaxy (SPE) annealing that promote Si regrowth in a high-C-concentration region, and the co-incorporation of phosphorus (P). These processes promoted markedly the recrystallization of C densely incorporated in an amorphous Si layer and realized e-Si:C S/D with high-crystallinity of strained Si:C layer while maintaining a high [C]sub at a high ratio of substitution with a high doping activation. © 2010 IEEE.

关键词： Recrystallization (metallurgy)

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Contributionxc of carbon to growth of strained silicon, dopant activation and diffusion in silicon

Contributionxc of carbon to growth of strained silicon, dopa...

引用

International Workshop on Junction technology

作者： Hiroshi Itokawa Advanced Unit Process Technology Department Device Process Development Center Corporate Research and Development Center Toshiba Corporation Yokohama Japan

关键词： Atomic layer deposition Silicon germanium Germanium silicon alloys Semiconductor films Epitaxial growth CMOSFETs CMOS technology Strain control Annealing Capacitive sensors

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Carbon incorporation into substitutional silicon site by car...

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International Workshop on Junction technology

作者： Hiroshi Itokawa Kiyotaka Miyano Yusuke Oshiki Hiroyuki Onoda Masahito Nishigoori Ichiro Mizushima Kyoichi Suguro Advanced Unit Process Technology Department Device Process Development Center Corporate Research and Development Center Toshiba Corporation Yokohama Japan System LSI Division Semiconductor Company Toshiba Corporation Yokohama Japan

ISBN: (纸本)9781424458660;9781424458691

Since the lattice constant of silicon-carbon (Si:C) is smaller than that of Si, Si:C embedded in the source and drain (e-Si:C S/D) can induce tensile stress in the channel and improve the electron mobility of n-metal-oxide-semiconductor field-effect transistors (nMOSFETs). In this research, C ion cryo implantation and a metastable recrystallization schemes employed to achieve strained Si:C layers with a high substitutionally incorporated carbon concentration ([C] sub ) at a high ratio of substitution, and a high doping activation were studied. we proposed the C cryo implantation for reduced implantation damage, the fast recrystallization by nonmelt laser annealing combined with solid phase epitaxy (SPE) annealing that promote Si regrowth in a high-C-concentration region, and the co-incorporation of phosphorus (P). These processes promoted markedly the recrystallization of C densely incorporated in an amorphous Si layer and realized e-Si:C S/D with high-crystallinity of strained Si:C layer while maintaining a high [C] sub at a high ratio of substitution with a high doping activation.

关键词： Silicon Ion implantation Metastasis Annealing Tensile stress Doping Lattices Electron mobility FETs MOSFETs

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