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检索条件"机构=Advanced Lithography Process Technology Department Device Process Development Center"

共 37 条记录，以下是21-30 订阅

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A practical application of Multiple Parameters Profile Characterization (MPPC) using CD-SEM on production wafers using Hyper-NA lithography

A practical application of Multiple Parameters Profile Chara...

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Metrology, Inspection, and process Control for Microlithography XXIII

作者： Ishimoto, T. Sekiguchi, K. Hasegawa, N. Watanabe, K. Laidler, D. Cheng, S. Semiconductor Equipment Business Group Hitachi High-Technologies Corporation 24-14 Nishi-Shimbashi 1-chome Minato-ku Tokyo 105-8717 Japan Japan Naka Application Center Naka Division Hitachi High-Technologies Corporation 882 Ichige Hitachinaka-shi Ibaraki 312-8504 Japan Hitachi High-Technologies Europe GmbH Europark Fichtenhain A12 47807 Krefeld Germany Lithography Department Silicon Process and Device Technology Division IMEC vzw Kapeldreef 75 B-3001 Leuven Belgium

ISBN: (纸本)9780819475251

With the improved resolution of immersion lithography by Hyper-NA (Numerical Aperture) and Low-kl scaling factor, lithographers face the problem of decreasing Depth of Focus and in turn reduced process latitude. It is important for high precision process monitoring the decrease in process latitude which comes with Hyper-NA and Low-kl, in order to be able to successfully introduce RET (Resolution Enhancement Techniques) lithography into high volume production. MPPC (Multiple Parameters Profile Characterization) is a function which provides the ability to extract pattern shape information from a measured e-beam signal. MPPC function becomes key technique of pattern profile verification by top down SEM images for the Hyper-NA lithography, for that reason it can be detected to relate to pattern profile change. In this work, we explored a practical application of MPPC function by making clear the relationship between MPPC indices and Litho parameters concerning specific lithography application. We performed the two kinds of experiment for verifying effectiveness of the MPPC function. First experiment explored printing image contrast by using the WB with exposure pattern shape change related from image printing condition. Second experiment explored pattern shape change due to resist contrast with changing the process conditions by using WB behavior. In consequence, we demonstrated a practical application of MPPC function by quantification using WB and assessed the process monitoring capability. Our challenge of this research is the practical application of the MPPC function on production wafers concerning specific lithography application. We believe that this application can be effectual in process monitoring and control for Hyper-NA lithography. ©2009 SPIE.

关键词： process control

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Feasibility of ultra-low k1 lithography for 28nm CMOS node

Feasibility of ultra-low k1 lithography for 28nm CMOS node

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Optical Microlithography XXII

作者： Mimotogi, Shoji Takahata, Kazuhiro Murakami, Takashi Nagahara, Seiji Takeda, Kazuhiro Satake, Masaki Kitamura, Yosuke Ojima, Tomoko Fujise, Hiroharu Seino, Yuriko Ema, Tatsuhiko Yonemitsu, Hiroki Takakuwa, Manabu Nakagawa, Shinichiro Kono, Takuya Asano, Masafumi Kyoh, Suigen Harakawa, Hideaki Nomachi, Akiko Ishida, Tatsuya Hasegawa, Shunsuke Miyashita, Katsura Tominaga, Makoto Inoue, Soichi Toshiba Corporation Semiconductor Company 8 Sinsugita-cho Isogo-ku Yokohama 235-8522 Japan System LSI Division 1 Toshiba Corporation Semiconductor Company 8 Sinsugita-cho Isogo-ku Yokohama 235-8522 Japan Advanced CMOS Technology Department SoC Research and Development Center Toshiba corporation 8 Sinsugita-cho Isogo-ku Yokohama 235-8522 Japan Process Tchnology Division NEC Electronics Corporation 8 Sinsugita-cho Isogo-ku Yokohama 235-8522 Japan

ISBN: (纸本)9780819475275

We have designed the lithography process for 28nm node logic devices using 1.35NA scanner. In the 28nm node, we face on the ultra-low k1 lithography in which dense pattern is affected by the mask topography effect and the oblique-incidence. Using the rigorous lithography simulation considering the electro-magnetic field, we have estimated accurately the feasibility of resolution of the minimum pitch required in 28nm node. The optimum mask plate and illumination conditions have been decided by simulation. The experimental results for 28nm node show that the minimum pitch patterns and minimum SRAM cell are clearly resolved by single exposure. © 2009 SPIE.

关键词： Logic devices

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Influence of moisture uptake in porous PAr film on electrical properties

Influence of moisture uptake in porous PAr film on electrica...

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24th Session of the advanced Metallization Conference 2007, AMC 2007

作者： Nakamura, N. Matsunaga, N. Watanabe, K. Miyajima, H. Enomoto, Y. Okada, N. Shibata, H. Advanced BEOL Technology Department Center for Semiconductor Research and Development Semiconductor Company Toshiba Corporation Process and Manufacturing Engineering Center Semiconductor Company Toshiba Corporation Semiconductor Technology Development Division Semiconductor Business Group Sony Corporation Advanced Device Development Division NEC Electronics Corporation 8 Shinsugita-cho Isogo-ku Yokohama Kanagawa 235-8522 Japan

ISBN: (纸本)9781558999923

In PAr/SiOC hybrid dual damascene structure, low-k polyarylene (PAr) films applied as trench layer material were damaged by plasma process and the damaged films absorbed moisture easily. The phenomenon was similar to that in the case of SiOC films applied as via layer material. It is confirmed that the moisture uptake degraded via properties. To achieve good electrical properties in the case of using porous PAr films, it is necessary to minimize the process damage. Optimization of metal dummy pattern is found to be one of the solutions to the issue of PAr damage and moisture uptake. © 2008 Materials Research Society.

关键词： Moisture

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Copper Line Resistance Control and Reliability Improvement by Surface Nitridation of Ti barrier Metal

Copper Line Resistance Control and Reliability Improvement b...

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IEEE International Conference on Interconnect technology

作者： A. Sakata S. Kato Y. Yano H. Toyoda T. Kawanoue M. Hatano J. Wada N. Yamada T. Oki H. Yamaguchi N. Nakamura K. Higashi M. Yamada T. Fujimaki M. Hasunuma Process & Manufacturing Engineering Center Semiconductor Company Toshiba Corporation Yokohama Kanagawa Japan Semiconductor Analysis and Evaluation Center Toshiba Nanoanalysis Corpration Yokohama Kanagawa Japan Advanced CMOS Technology Department SoC Research & Development Center Semiconductor Company Toshiba Corporation Yokohama Kanagawa Japan System LSI Division I Semiconductor Company Toshiba Corporation Yokohama Kanagawa Japan

This paper proposes highly reliable, low resistance and cost effective Cu interconnect system for 45nm CMOS device and beyond. Overhang formation and Cu line resistance increase by deposition process variation are serious problems for titanium (Ti) barrier metal (BM). Overhang reduction by surface nitridation of Ti BM has been successfully demonstrated. It has been clarified that Cu resistivity increase with Ti BM is due to insufficient Cu grain growth, not reaction between Ti and Cu. Surface nitridation contributes to Cu line resistance reduction by changing grain growth behavior. Moreover, it also improves oxidation endurance of the BM caused by absorbed moisture from porous low-k ILD. It is concluded that surface nitridation of Ti BM is promising approach as Cu barrier metal for 45nm device and beyond to fabricate Cu interconnect with controlled resistance and high reliability.

关键词： Surface resistance Copper Electrical resistance measurement Conductivity Moisture Grain boundaries Filling Testing Semiconductor device reliability CMOS process

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development of high performance multi-layer process with H2 plasma hardening

Development of high performance multi-layer process with H2 ...

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55th Society of Polymer Science Japan Symposium on Macromolecules

作者： Ishibashi, Takeo Ono, Yoshiharu Yamaguchi, Atsumi Hanawa, Tetsuro Tadokoro, Masahiro Yoshikawa, Kazunori Yonekura, Kazumasa Okumura, Haruki Matsunobe, Tsuyoshi Fujii, Yasushi Tanaka, Takeshi Terai, Mamoru Kumada, Teruhiko Renesas Technology Corp. Process Development Dept. 664-0005 Hyogo Japan Materials Science Lab. Toray Research Center Inc. 3-3-7 Otsu Shiga 525-8567 Japan Tokyo Ohka Kogyo Co. Ltd. Advanced Material Development Division 1 Research and Development Department 1590Tabata Samukawa-machi Koza-gun Kanagawa 253-0014 Japan Advanced Tech. R/D Center Mitsubishi Electric Corp. 8-1-1 Tsukaguchi-Honmachi Amagasaki Hyogo 661-8661 Japan

In the device manufacture after 45nm node utilization of a high precision carbon hard mask (C-HM) process is an important issue. We examined additional H2 plasma hardening treatment to the bottom organic layer in a conventional multi-layer resist process. Improved results in LWR caused by etching, which is called "wiggling", were obtained. Chemical constitution was analyzed to understand the mechanism of improvement. Analyses were carried out using GSP+FTIR and Raman spectroscopy. This hardening process will provide a very versatile C-HM process that is useful not only FEOL but also BEOL, which includes Dual Damascene process with via hole filling by the bottom organic layer.

关键词： Multilayers

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A Study of Water Absorption Induced-Dielectric Constant Increase and Its Suppression on Copper Damascene Interconnect Structure with Porous Low-k (k=2.3) Dielectrics

A Study of Water Absorption Induced-Dielectric Constant Incr...

引用

IEEE International Conference on Interconnect technology

作者： N. Nakamura N. Matsunaga K. Higashi M. Shimada H. Miyajima M. Yamada Y. Enomoto T. Hasegawa H. Shibata Advanced CMOS Technology Department Toshiba Corporation Yokohama Japan Advanced CMOS Technology Department Toshiba Corporation Process & Manufacturing Engineering Center Toshiba Corporation Yokohama Japan System LSI Division I Toshiba Corporation Yokohama Japan Semiconductor Technology Development Group Sony Corporation Yokohama Kanapwa Japan

A key technology for realizing an effective k-value (keff) required for 45nm node is proposed. We studied the behavior of effective dielectric constant derived from capacitance of double-level copper interconnect wires with porous low-k material in detail. The porous low-k materials easily absorb moisture due to process damage and the dielectric constant drastically increases. We have confirmed that if moisture-controlled robust process integration is performed, a reasonably effective dielectric constant (2.8) is obtained corresponding to the ideal bulk k-value (2.4). However, when the sealing of passivation films is broken, the effective dielectric constant increases to the level derived from that of the damaged blanket film. In order to ensure a target capacitance of copper interconnect wire with porous low-k material, it is indispensable to perfectly seal a whole device area from moisture uptake

关键词： Absorption Copper Dielectric constant Dielectric materials Capacitance Moisture Wires Robustness Passivation Sealing materials

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A study of water absorption induced-dielectric constant increase and its suppression on copper damascene interconnect structure with porous low-k (k=2.3) dielectrics

A study of water absorption induced-dielectric constant incr...

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9th International Interconnect technology Conference (IITC)

作者： Nakamura, N. Matsunaga, N. Higashi, K. Shimada, M. Miyajima, H. Yamada, M. Enomoto, Y. Hasegawa, T. Shibata, H. Advanced CMOS Technology Department SoC R and D Center Toshiba Corporation Isogo-ku Yokohama Kanagawa 235-8522 8 Shinsugita-cho Japan Process and Manufacturing Engineering Center Semiconductor Company Toshiba Corporation Isogo-ku Yokohama Kanagawa 235-8522 8 Shinsugita-cho Japan System LSI Division I Semiconductor Company Toshiba Corporation Isogo-ku Yokohama Kanagawa 235-8522 8 Shinsugita-cho Japan Semiconductor Technology Development Group Semiconductor Business Unit Sony Corporation Isogo-ku Yokohama Kanagawa 235-8522 8 Shinsugita-cho Japan

ISBN: (纸本)1424401038

A key technology for realizing an effective k-value (keff) required for 45nm node is proposed. We studied the behavior of effective dielectric constant derived from capacitance of double-level copper interconnect wires with porous low-k materials in detail. The porous low-k materials easily absorb moisture due to process damage and the dielectric constant drastically increases. We have confirmed that if moisture-controlled robust process integration is performed, a reasonably effective dielectric constant (2.8) is obtained corresponding to the ideal bulk k-value (2.4). However, when the sealing of passivation films is broken, the effective dielectric constant increases to the level derived from that of the damaged blanket film. In order to ensure a target capacitance of copper interconnect wire with porous low-k material, it is indispensable to perfectly seal a whole device area from moisture uptake.

关键词： Capacitance

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Fabrication of 3D trench PZT capacitors for 256Mbit FRAM device application

Fabrication of 3D trench PZT capacitors for 256Mbit FRAM dev...

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International Electron devices Meeting (IEDM)

作者： June-Mo Koo Bum-Seok Seo Sukpil Kim Sangmin Shin Jung-Hyun Lee Hionsuck Baik Jang-Ho Lee Jun Ho Lee Byoung-Jae Bae Ji-Eun Lim Dong-Chul Yoo Soon-Oh Park Hee-Suk Kim Hee Han Sunggi Baik Jae-Young Choi Yong Jun Park Youngsoo Park Nano Devices Laboratory Samsung Advanced Institute of Technology Yongin si South Korea Nano Fabrication Center Samsung Advanced Institute of Technology Yongin si South Korea AE Center Samsung Advanced Institute of Technology Yongin si South Korea Process Development Team Semiconductor R&D Division Samsung Electronics Company Limited Yongin si South Korea Department of Materials Science and Engineering Pohang University of Science and Technology Pohang South Korea Pohang Accelerator Laboratory Pohang University of Science and Technology Pohang South Korea

ISBN: (纸本)078039268x

We fabricated trench PbZr x Ti 1-x O 3 (PZT) capacitors that can be used in 256Mbit 1T-1C FRAM devices. The capacitor has 0.25mum diameter and 0.4mum depth. Three layers, Ir(20nm)/PZT(60nm)/Ir(20nm), were deposited in SiO 2 trench holes by ALD and MOCVD. Both columnar and granular grains were formed on the sidewalls of the trench capacitors, and their relative portion had strong size dependence. The trench capacitors with more columnar PZT grains showed good switching behavior under 2.1V external bias and 19 to 24 muC/cm 2 remnant polarization

关键词： Fabrication Capacitors Random access memory Ferroelectric films Nonvolatile memory Polarization Materials science and technology Laboratories MOCVD Ferroelectric materials

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A proper lifetime-prediction method of PMOSFET with 1.1 nm gate dielectrics in the lower testing voltage region

A proper lifetime-prediction method of PMOSFET with 1.1 nm g...

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Annual International Symposium on Reliability Physics

作者： N. Tamura M. Kase Process Development Department Advanced device development Division Akiruno Technology Center Fujitsu Laboratories Limited Akiruno Tokyo Japan

A prediction method of time dependent dielectric breakdown (TDDB) lifetime on P-type metal-oxide-semiconductor field effect transistors (PMOSFETs) with 1.1 nm gate dielectrics is studied. Prediction of a voltage dependence of TDDB lifetime was newly proposed using a defect generation probability (P/sub G/), which incorporates both scattering rate of hole and valence band electrons. It is found that the lifetime predicted with P/sub G/ is about ten times longer than that with only high testing voltage. This is the reason why both the channel hole and valence band tunneling electron (VBE) influence this probability, especially VBE is rapidly decreased with a low testing voltage below -1.5 V. Our model based on the newly proposed PG enables us to estimate the proper TDDB lifetime of PMOSFETs, and predicts a power-law voltage dependence on inversion mode.

关键词： MOSFET circuits Life testing Charge carrier processes Prediction methods Dielectric breakdown FETs Scattering Tunneling Low voltage Predictive models

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device performance of sub-50 nm CMOS with ultra-thin plasma nitrided gate dielectrics

Device performance of sub-50 nm CMOS with ultra-thin plasma ...

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International Electron devices Meeting (IEDM)

作者： S. Inaba T. Shimizu S. Mori K. Sekine K. Saki H. Suto H. Fukui M. Nagamine M. Fujiwara T. Yamamoto M. Takayanagi I. Mizushima K. Okano S. Matsuda H. Oyamatsu Y. Tsunashima S. Yamada Y. Toyoshima H. Ishiuchi SoC Research & Development Center Toshiba Corporation Semiconductor Company Yokohama Japan SoC Research & Development Center Process & Manufacturing Engineering Center Toshiba Corporation Semiconductor Company Yokohama Japan Advanced LSI Technology Laboratories Corporate Research and Development Toshiba Corporation Yokohama Japan Advanced Logic Technology Department System LSI Division Toshiba Corporation Semiconductor Company Yokohama Japan

In this paper, the physical and electrical characteristics of ultra-thin plasma nitrided gate dielectrics are reported, aiming for sub-50 nm gate length CMOS applications. The impact of plasma nitridation conditions on DC characteristics was investigated extensively by changing nitrogen plasma pressure, plasma immersion time, or plasma generation power. NBTI has been also investigated and the lifetime at 105/spl deg/C and 0.85 V operation is estimated to be about 10 years. The final current drives of 690 /spl mu/A//spl mu/m for nFET and 301 /spl mu/A//spl mu/m for pFET at Vdd = 0.85 V (Ioff = 100 nA//spl mu/m) have been achieved in sub-50 nm CMOS with optimized plasma nitrided gate dielectric with EOT <1.2 nm.

关键词： Plasma devices Dielectric devices Plasma applications Plasma properties Electric variables Nitrogen DC generators Character generation Power generation Niobium compounds

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