As the mobile electronics equipment moves toward higher performance and miniaturizing, each IC package is required to be stacked for saving a package mounting area on a system board. This paper describes a newly devel...
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ISBN:
(纸本)0780370384
As the mobile electronics equipment moves toward higher performance and miniaturizing, each IC package is required to be stacked for saving a package mounting area on a system board. This paper describes a newly developed 3-dimensional module package using the technology of the silicon device thinning, micro flip chip bonding and two types of via connection of print circuit board for vertical wirings. These technology has realized the high density packaging of over 4 ICs stacking for practical use.
In the rapid evolution of VLSI technology toward smaller geometries and increased levels of chip integration, minimum features of 0.18 μm are already being mass produced, and feature sizes of 0.13 μm are being devel...
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In the rapid evolution of VLSI technology toward smaller geometries and increased levels of chip integration, minimum features of 0.18 μm are already being mass produced, and feature sizes of 0.13 μm are being developed. At the same time, 300-mm fab lines are being built, and this is driving a demand for new etching technologies that support smaller tolerances and larger wafer sizes. Insulation layer etching demands good selectivity between mask and substrate and high-aspect vertical processing to deal with increasing aspect ratios and thinner mask thicknesses that go along with shrinking geometries and increasing integration levels. Meanwhile, damascene processes (electroplating for chip interconnects) using a combination of low-κ (low dielectric constant) insulation materials and Cu interconnects are being investigated, and etchers capable of processing these structures will be in great demand. To address these issues, we have developed an insulation layer etcher that uses UHF-ECR (ultra high frequency electron cyclotron resonance) plasma. The unique advantages of this approach are that it enables good control over CF 2/F radicals, an important etchant for selectivity and high-aspect openings, and good control over the ratio of ions to CF2, which is important in achieving vertical profiles. This etcher is capable of (1) producing stable and uniform medium-to-high density plasmas over a large area at low-to-medium pressures using UHF wave (450 MHz) ECR, and (2) increasing the doubled-near-surface effect* and good radical ratio control through control over the UHF wave flat antenna and antenna bias. Taken together, these capabilities amount to a powerful plasma process tool able to process fine features below 0.13 μm.
In the 0.1 μm process generation, we are progressing toward what is being called the "system on a chip." The promotion of that trend requires more than the LSI technology for increasing the integration scal...
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In the 0.1 μm process generation, we are progressing toward what is being called the "system on a chip." The promotion of that trend requires more than the LSI technology for increasing the integration scale of CMOS (complementary metal-oxide semiconductor) devices as suggested in the ITRS (International technology Roadmap for Semiconductors). Also required is progress in the development of new materials for finer patterning and core integration technology through intimate cooperation of technologies for design, device/process, and manufacturing and inspection equipment. That will make it possible to provide the customer with the best solution from among diverse goals and approaches. The 0.1 μm-generation LSI chips feature high integration scale, with CMOS gate lengths of 0.1 μm or less, the integration of DRAM (dynamic random access memory), flash memory, BiCMOS (bipolar CMOS), analog cores, etc., and eight or nine layers of multi-layer wiring. Another feature is the full use of new materials, of which high- κ (dielectric constant) gate insulation films, copper wiring and low-κ interlayer films are typical. Such issues in LSI fabrication and inspection technology can be classified into those related to processes for (1) larger integration scale, (2) use of new materials, (3) core mixing and those related to production technology for (4) shorter development turnaround time (TAT) and (5) lower cost.
Body-contacted short channel partially depleted nMOS Sal devices exhibit higher output impedance and intrinsic gain than their bulk silicon counterparts by nearly a factor of 2 for most body-to-source bias conditions....
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ISBN:
(纸本)2863322451
Body-contacted short channel partially depleted nMOS Sal devices exhibit higher output impedance and intrinsic gain than their bulk silicon counterparts by nearly a factor of 2 for most body-to-source bias conditions. This enhancement is lost when the Sal device moves into the transition region between partially depleted and folly depleted operation, at which point the output impedance and the intrinsic gain approach that of bulk silicon.
In this work we demonstrate the application of tunneling spectroscopy to the silicon Metal-Oxide-Semiconductor system. As an electrical characterization method, this technique allows for the direct study of the struct...
In this work we demonstrate the application of tunneling spectroscopy to the silicon Metal-Oxide-Semiconductor system. As an electrical characterization method, this technique allows for the direct study of the structure of ultra-thin gate oxides in standard as-fabricated test structures, and their dependence upon processing and electrical stress.
作者：
Deura, MNara, YYamazaki, TGotoh, KOhtake, FKurata, HSugii, TFujitsu Laboratories Ltd.
Atsugi Japan 243-01 Graduated from Aoyamagakuin University
Dept. of Electrical and Electronic Engineering in 1991 and completed the MS course at Tokyo Institute of Technology in 1993. He then joined Fujitsu Laboratories. Since then he has been engaged in research on deep submicron CMOS. He is currently in ULSI Process Department. He is a member of the Applied Physics Society. Graduated from Tokyo Institute of Technology
Dept. of Electronic Engineering in 1980 and completed the doctoral course in 1985. He then joined Fujitsu Laboratories. Since then he has been engaged in research on ULSI process and devices. He holds a doctorate in engineering. He is now a senior researcher in the ULSI Process Department. He is a member of the Applied Physics Society. Graduated from Keio University
Dept. of Electrical Engineering in 1981 and completed the MS course in 1983. He then joined Fujitsu Laboratories. Since then he has been engaged in research on ULSI processes and devices. He is now in the Process Development Department Fujitsu Electronic Device Promotion Center. He is a member of the Applied Physics Society. Graduated from Tohoku University
Dept. of Electronic Engineering in 1989 and completed the MS course in 1991. He joined Fujitsu Laboratories in that year. Since then he has been engaged in research on silicide processes for deep submicron CMOS. He is now in the ULSI Process Department. He is a member of the Applied Physics Society. Graduated from Tohoku University
Dept. of Electronic Engineering in 1988 and completed the MS course in 1990. He then joined Fujitsu Laboratories. Since then he has been engaged in research on ULSI processes and devices. He is now in the ULSI Process Department. He is a member of the Applied Physics Society. Graduated from the University of Tokyo
Dept. of Electronic Engineering in 1987 and completed the doctoral course in 1993. He then joined Fujitsu Laboratories. Since then he has been engaged in research on deep submicron CMOS. He is now
Integrated circuits with 1GHz logic, 1G bit DRAM, and 1G transistors, together with the CMOS technology with a gate length of less than 0.2 mu m are the ingredients of the ''Giga-Era.'' However, in ord...
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Integrated circuits with 1GHz logic, 1G bit DRAM, and 1G transistors, together with the CMOS technology with a gate length of less than 0.2 mu m are the ingredients of the ''Giga-Era.'' However, in order to integrate these billions of MOSs at giga-frequencies, the problem of the power consumption cannot be avoided. It is a common practice to cope with this problem by reducing the power supply voltage. In deep submicron MOS, although the basic gate delay is not likely to degrade as the power supply voltage is reduced, it is necessary to set a low threshold value (V-th) within the wafer plane with reduced parasitic devices, if the absolute current values become important, as in the interconnect load. However, reliability problems involving the short-channel effect and hot carriers then cannot be avoided. This paper describes the use of the cobalt silicide process and shallow extension structure of the source/drain to reduce the parasitic resistance. It is also shown that setting a low V-th with fewer fluctuations is possible by combining the double-side-wall process and the counter-dose process. By means of the above process, deep submicron CMOS with low parasitic resistance and low V-th can be fabricated.
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