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IEEE Biomedical Circuits and systems (BIOCAS)

作者： Jaeeun Jang Hyunwoo Cho Hoi-Jun Yoo Department of EE Korea Advanced Institute of Science and Technology (KAIST) Daejeon Republic of Korea System LSI Division Samsung Semiconductor Hwaseong Republic of Korea

In this paper, a new Body Channel Communication (BCC) transceiver (TRX) that can support IEEE 802.15 HBC PHY standard and high-speed data transmission is proposed. First, the sinusoidal-modulated transmitter is proposed for the standard mode transceiver, and it can reduce filtering power overhead 35%. Second, high-speed TRX with dual-band Quadrature Phase Shift Keying (QPSK) modulation is proposed to increase system data rate and bandwidth efficiency. In third, on-chip RC duplexer is integrated for full-duplex function. The transceiver is implemented with 180nm CMOS process. As a result, the proposed transceiver satisfies high scalability of WBAN standard as well as high data rate requirements in designated multimedia applications.

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Comprehensive study of systematic and random variation in gate-induced drain leakage for LSTP applications

Comprehensive study of systematic and random variation in ga...

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作者： Shimizu, S. Aikawa, H. Okamoto, S. Kakehi, K. Ohsawa, K. Yoshimura, H. Asami, T. Ishimaru, K. Advanced Logic Technology Department System LSI Division Toshiba Corporation Semiconductor Company 3500 Matsuoka Oita 870-0197 Japan

ISBN: (纸本)9784863481640

systematic and random variability of Gate-Induced Drain Leakage (GIDL) current have been studied for the first time. Trap-assisted tunneling current shows more instability than band-to-band tunneling current in every kinds of variations resulting from high sensitivity of the traps to impurities under MOSFET channel. © 2011 JSAP (Japan Society of Applied Physi.

关键词： Sensitivity analysis

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Comprehensive study of systematic and random variation in Gate-Induced Drain Leakage for LSTP applications

Comprehensive study of systematic and random variation in Ga...

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Symposium on Vlsi technology

作者： S. Shimizu H. Aikawa S. Okamoto K. Kakehi K. Ohsawa H. Yoshimura T. Asami K. Ishimaru Advanced Logic Technology Department System LSI Division Toshiba Corporation Semiconductor Company Oita Japan

关键词： logic gates Tunneling MOS devices systematics Current measurement Junctions Very large scale integration

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Carbon incorporation into substitutional silicon site by carbon cryo ion implantation and metastable recrystallization annealing as stress technique in n-metal-oxide-semiconductor field-effect transistor

Carbon incorporation into substitutional silicon site by car...

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10th International Workshop on Junction technology, IWJT-2010

作者： Itokawa, Hiroshi Miyano, Kiyotaka Oshiki, Yusuke Onoda, Hiroyuki Nishigoori, Masahito Mizushima, Ichiro Suguro, Kyoichi Advanced Unit Process Technology Department Device Process Development Center Corporate Research and Development Center Japan System LSI Division Semiconductor Company Toshiba Corporation 8 Shinsugita-cho Isogo-ku Yokohama 235-8522 Japan

ISBN: (纸本)9781424458691

Since the lattice constant of silicon-carbon (Si:C) is smaller than that of Si, Si:C embedded in the source and drain (e-Si:C S/D) can induce tensile stress in the channel and improve the electron mobility of n-metal-oxide- semiconductor field-effect transistors (nMOSFETs). In this research, C ion cryo implantation and a metastable recrystallization schemes employed to achieve strained Si:C layers with a high substitutionally incorporated carbon concentration ([C]sub) at a high ratio of substitution, and a high doping activation were studied. we proposed the C cryo implantation for reduced implantation damage, the fast recrystallization by nonmelt laser annealing combined with solid phase epitaxy (SPE) annealing that promote Si regrowth in a high-C-concentration region, and the co-incorporation of phosphorus (P). These processes promoted markedly the recrystallization of C densely incorporated in an amorphous Si layer and realized e-Si:C S/D with high-crystallinity of strained Si:C layer while maintaining a high [C]sub at a high ratio of substitution with a high doping activation. © 2010 IEEE.

关键词： Recrystallization (metallurgy)

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Carbon incorporation into substitutional silicon site by car...

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International Workshop on Junction technology

作者： Hiroshi Itokawa Kiyotaka Miyano Yusuke Oshiki Hiroyuki Onoda Masahito Nishigoori Ichiro Mizushima Kyoichi Suguro Advanced Unit Process Technology Department Device Process Development Center Corporate Research and Development Center Toshiba Corporation Yokohama Japan System LSI Division Semiconductor Company Toshiba Corporation Yokohama Japan

ISBN: (纸本)9781424458660;9781424458691

Since the lattice constant of silicon-carbon (Si:C) is smaller than that of Si, Si:C embedded in the source and drain (e-Si:C S/D) can induce tensile stress in the channel and improve the electron mobility of n-metal-oxide-semiconductor field-effect transistors (nMOSFETs). In this research, C ion cryo implantation and a metastable recrystallization schemes employed to achieve strained Si:C layers with a high substitutionally incorporated carbon concentration ([C] sub ) at a high ratio of substitution, and a high doping activation were studied. we proposed the C cryo implantation for reduced implantation damage, the fast recrystallization by nonmelt laser annealing combined with solid phase epitaxy (SPE) annealing that promote Si regrowth in a high-C-concentration region, and the co-incorporation of phosphorus (P). These processes promoted markedly the recrystallization of C densely incorporated in an amorphous Si layer and realized e-Si:C S/D with high-crystallinity of strained Si:C layer while maintaining a high [C] sub at a high ratio of substitution with a high doping activation.

关键词： Silicon Ion implantation Metastasis Annealing Tensile stress Doping Lattices Electron mobility FETs MOSFETs

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Compact model for layout dependent variability

Compact model for layout dependent variability

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International Electron Devices Meeting (IEDM)

作者： H. Aikawa T. Sanuki A. Sakata E. Morifuji H. Yoshimura T. Asami H. Otani H. Oyamatsu Advanced Logic Technology Department System LSI Division Toshiba Corporation Semiconductor Company Oita Japan

ISBN: (纸本)9781424456390

We have developed a compact model which deals with MOSFET characteristic variations arising from design layout dependences. It treats many stress related variations and their interactions that are especially important in 45 nm technology node. It is demonstrated that the model can predict MOSFET characteristics used in standard cells with high accuracy.

关键词： Semiconductor device modeling Large scale integration MOSFET circuits Stress CMOS technology Predictive models DSL Manufacturing logic Electronic mail

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Publisher's Note: Substrate Dependent Growth Rate of Plasma-Enhanced Atomic Layer Deposition of Titanium Oxide Using N2O Gas [ Electrochem. Solid-State Lett. , 13 , G13 (2010) ]

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Electrochemical and Solid State Letters 2010年第4期13卷

作者： Seok-Jun Won Sungin Suh Sang Woon Lee Gyu-Jin Choi Cheol Seong Hwang Hyeong Joon Kim Department of Materials Science and Engineering and Inter-university Semiconductor Research Center Seoul National University Seoul 151-744 Korea Samsung Electronics Company Limited System-LSI Division Advanced Technology Development Team Yongin Kyungki 449-900 Korea

Abstract not Available.

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Feasibility of ultra-low k1 lithography for 28nm CMOS node

Feasibility of ultra-low k1 lithography for 28nm CMOS node

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Optical Microlithography XXII

作者： Mimotogi, Shoji Takahata, Kazuhiro Murakami, Takashi Nagahara, Seiji Takeda, Kazuhiro Satake, Masaki Kitamura, Yosuke Ojima, Tomoko Fujise, Hiroharu Seino, Yuriko Ema, Tatsuhiko Yonemitsu, Hiroki Takakuwa, Manabu Nakagawa, Shinichiro Kono, Takuya Asano, Masafumi Kyoh, Suigen Harakawa, Hideaki Nomachi, Akiko Ishida, Tatsuya Hasegawa, Shunsuke Miyashita, Katsura Tominaga, Makoto Inoue, Soichi Toshiba Corporation Semiconductor Company 8 Sinsugita-cho Isogo-ku Yokohama 235-8522 Japan System LSI Division 1 Toshiba Corporation Semiconductor Company 8 Sinsugita-cho Isogo-ku Yokohama 235-8522 Japan Advanced CMOS Technology Department SoC Research and Development Center Toshiba corporation 8 Sinsugita-cho Isogo-ku Yokohama 235-8522 Japan Process Tchnology Division NEC Electronics Corporation 8 Sinsugita-cho Isogo-ku Yokohama 235-8522 Japan

ISBN: (纸本)9780819475275

We have designed the lithography process for 28nm node logic devices using 1.35NA scanner. In the 28nm node, we face on the ultra-low k1 lithography in which dense pattern is affected by the mask topography effect and the oblique-incidence. Using the rigorous lithography simulation considering the electro-magnetic field, we have estimated accurately the feasibility of resolution of the minimum pitch required in 28nm node. The optimum mask plate and illumination conditions have been decided by simulation. The experimental results for 28nm node show that the minimum pitch patterns and minimum SRAM cell are clearly resolved by single exposure. © 2009 SPIE.

关键词： logic devices

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Variability aware modeling and characterization in standard cell in 45 nm CMOS with stress enhancement technique

Variability aware modeling and characterization in standard ...

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2008 Symposium on Vlsi technology Digest of Technical Papers, VlsiT

作者： Aikawa, H. Morifuji, E. Sanuki, T. Sawada, T. Kyoh, S. Sakata, A. Ohta, M. Yoshimura, H. Nakayama, T. Iwai, M. Matsuoka, F. Advanced Logic Technology Dept. System LSI Division Toshiba Corporation Semiconductor Company 8 Shinsugita-cho Isogo-ku Yokohama 235-8522 Japan Process and Manufacturing Engineering Center Toshiba Corporation Semiconductor Company

ISBN: (纸本)9781424418053

Gate density is ultimately increased to 2100 kGates/mm2 by pushing the critical design rules without increasing the circuit margin in 45 nm technology. Layout dependences for stress enhanced MOSFET including contact positioning, 2nd neighboring poly effect, and bent diffusion are accurately modeled for the first time. With the constructed design flow, gate length change of -2.8% to +3.6% and Idsat change of -10% to +14% are removed from uncertain margin in 45 nm corner libraries. © 2008 IEEE.

关键词： CMOS integrated circuits

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Variability Aware Modeling and Characterization in Standard Cell in 45nm CMOS with Stress Enhancement Technique

Variability Aware Modeling and Characterization in Standard ...

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Symposium on Vlsi technology

作者： H. Aikawa E. Morifuji T. Sanuki T. Sawada S. Kyoh A. Sakata M. Ohta H. Yoshimura T. Nakayama M. Iwai F. Matsuoka Advanced Logic Technology Dept. System LSI Division Toshiba Corporation Semiconductor Company 8 Shinsugita-cho Isogo-ku Yokohama 235-8522 Japan

ISBN: (纸本)9781424418022

Gate density is ultimately increased to 2100kGates/mm{sup}2 by pushing the critical design rules without increasing the circuit margin in 45nm technology. Layout dependences for stress enhanced MOSFET including contact positioning, 2nd neighboring poly effect, and bent diffusion are accurately modeled for the first time. With the constructed design flow, gate length change of -2.8% to +3.6% and Idsat change of -10% to +14% are removed from uncertain margin in 45nm corner libraries.

关键词： Design flow Batteries metal-oxide-semiconductor field effect transistors Complementary Metal Oxide Semiconductor Awareness Tumor margin status Stress (mechanics) Stressing

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