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检索条件"机构=Advanced Memory Process Development Center Memory Division"

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Comparison of electrical characteristics of back- and top-gate Si nanowire field-effect transistors

Comparison of electrical characteristics of back- and top-ga...

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IEEE Nanotechnology Materials and Devices Conference (NMDC)

作者： Changjoon Yoon Kihyun Keem Jeongmin Kang Dong-Young Jeong Moon-Sook Lee In-Seok Yeo U-In Chung Joo-Tae Moon Sangsig Kim Department of Electrical Engineering and Institute for Nano Science Korea University Seoul South Korea Process Development Team Memory Division R&D Center Samsung Electronics Company Limited Yongin si Gyeonggi South Korea

Top-gate(TG) field effect transistors (FETs) with channels composed of Si nanowires were successfully fabricated in this study using photolithographic processes. In the TG FETs fabricated on oxidized Si substrates, the channels composed of Si nanowires with diameters of about 100 nm with natural SiO 2 . The surfaces of the Si nanowires with natural SiO 2 were covered with the gate metal to form TG FETs.

关键词： Electric variables FETs Electrodes Nanoscale devices Fabrication Dielectric materials Gold Voltage Boron Powders

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Reliability issues and models of sub-90nm NAND flash memory cells

Reliability issues and models of sub-90nm NAND flash memory ...

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ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology

作者： Yang, Hong Kim, Hyunjae Park, Sung-Il Kim, Jongseob Lee, Sung-Hoon Choi, Jung-Ki Hwang, Duhyun Kim, Chulsung Park, Mincheol Lee, Keun-Ho Park, Young-Kwan Shin, Jai Kwang Kong, Jeong-Taek Memory Division CAE Team Samsung Electronics Co. Ltd. San #16 Banwol-Dong Hwasung-City Gyeonggi-Do 445-701 Korea Republic of Nano CSE Project Team Samsung Advanced Institute of Technology Korea Republic of R and D TEST Engineering Group Samsung Electronics Co. Ltd. Korea Republic of Process Development Team Samsung Electronics Co. Ltd. Korea Republic of Flash Process Architecture Team Semiconductor Business Samsung Electronics Co. Ltd. Korea Republic of

ISBN: (纸本)1424401615

The reliability issues, including 100k cycle's endurance and 2 hours high temperature storage (HTS: 150°C, 200° and 250°C) of sub-90nm NAND Flash cells, are studied. Furthermore, the trap generation models in endurance and interface trap recovery model in HTS are proposed. Endurance characteristics show that the interface trap and bulk trap generation have a power-dependence on program/erase cycle count (ΔNit, ΔNot, ∝ cycle). The exponent of interface trap generation both program and erase are 0.62;while in bulk trap generation, the exponent for the cycle count is 0.30, which is extracted only from the erased cells due to varying stored charges of programmed cells during tunnel oxide degradation. The HTS characteristics show that the interface trap recovery and electron-detrapping are the major mechanisms for sub-90nm NAND Flash memory, while stress induced leakage current (SILC) is almost negligible. Thus, based on the reaction-diffusion (R-D) model and Arrhenius approximation, the simplified interface recovery model in HTS is proposed as: dNit/N it=-k0·exp(-Ea/kBT) ·dt. © 2006 IEEE.

关键词： Electric batteries

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Reliability Issues and Models of sub-90nm NAND Flash memory Cells

Reliability Issues and Models of sub-90nm NAND Flash Memory ...

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2006 8th International Conference on Solid-State and Integrated Circuit Technology

作者： Hong Yang Hyunjae Kim Sung-il Park Jongseob Kim Sung-Hoon Lee Jung-Ki Choi Duhyun Hwang Chulsung Kim Mincheol Park Keun-Ho Lee Young-Kwan Park Jai Kwang Shin Jeong-Taek Kong CAE Team Memory DivisionSemiconductor BusinessSamsung Electronics Co.Ltd.San Nano CSE Project Team Samsung Advanced Institute of Technology R&D TEST Engineering Group Samsung Electronics Co.Ltd. Process Development Team Samsung Electronics Co.Ltd. Flash Process Architecture Team Semiconductor BusinessSamsung Electronics Co.Ltd.

ISBN: (纸本)1424401607

The reliability issues,including 100k cycle's endurance and 2 hours high temperature storage（HTS:150℃, 200℃and 250℃） of sub-90nm NAND Flash cells,are ***,the trap generation models in endurance and interface trap recovery model in HTS are *** characteristics show that the interface trap and bulk trap generation have a power-dependence on program/erase cycle count(△N,△N∝cycle^m).The exponent of interface trap generation both program and erase are 0.62;while in bulk trap generation,the exponent for the cycle count is 0.30,which is extracted only from the erased cells due to varying stored charges of programmed cells during tunnel oxide *** HTS characteristics show that the interface trap recovery and electron-detrapping are the major mechanisms for sub-90nm NAND Flash memory,while stress induced leakage current（SILC） is almost ***,based on the reaction-diffusion （R-D）model and Arrhenius approximation,the simplified interface recovery model in HTS is proposed as:dN/N=-k·exp（-E/kT）.dt.

关键词： HTS Reliability Issues and Models of sub-90nm NAND Flash memory Cells

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Highly scalable on-axis confined cell structure for high density PRAM beyond 256Mb

Highly scalable on-axis confined cell structure for high den...

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2005 Symposium on VLSI Technology

作者： Cho, S.L. Yi, J.H. Ha, Y.H. Kuh, B.J. Lee, C.M. Park, J.H. Nam, S.D. Horii, H. Cho, B.O. Ryoo, K.C. Park, S.O. Kim, H.S. Chung, U.-In Moon, J.T. Ryu, B.I. Process Development Team Memory Division Samsung Electronics Co. Ltd. San#24 Yongin-City Gyeonggi-Do 449-711 Korea Republic of Advanced Technology Development Memory Division Samsung Electronics Co. Ltd. San#24 Yongin-City Gyeonggi-Do 449-711 Korea Republic of

ISBN: (纸本)4900784001

We firstly fabricated on-axis confined structure and evaluated based on 64Mb PRAM with 0.12μm-CMOS technologies. Ge2Sb2Te 5 was confined within small pore, which resulted in low writing current of 0.4mA. The pore is on-axis with upper and lower contacts, which leads to good scalability of PRAM above 256Mb. The confined structure was relatively insensitive to small cell edge damage effect. The on-axis confined structure is a promising candidate for high density PRAM due to low writing current, good scalability, and insensitiveness to edge damage.

关键词： Random access storage

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Effects of abrasive size and surfactant concentration in ceria slurry for shallow trench isolation CMP

Effects of abrasive size and surfactant concentration in cer...

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10th International Chemical-Mechanical Planarization for ULSI Multilevel Interconnection Conference, CMP-MIC 2005

作者： Park, Hyung-Soon Jung, Jong-Goo Park, Jum-Yong Shin, Jong-Han Ryu, Cheol-Hwi Sohn, Hyun-Chul Kang, Hyun-Goo Katho, Takeo Park, Jae-Gun Advanced Process Department 3 Memory Research and Development Division Hynix Semiconductor Inc. San 136-1 Ami-Ri Ichon-Si Kyunggi-Do 467-701 Korea Republic of Nano-SOI Process Laboratory Hanyang University 17 Haengdang-Dong Seoungdong-Gu Seoul 133-791 Korea Republic of

The effects of the abrasive morphology and surfactant concentration in ceria slurry on removal rates for silicon oxide and silicon nitride films were investigated through a systematic chemical-mechanical-polishing (CMP) experiment. We found that the smaller the abrasives were, the more quickly the removal rates for both oxide and nitride films decreased with increasing surfactant concentration. This result was qualitatively explained by a model in which abrasive particles move through a viscous layer caused by surfactant adsorption onto the film surface being polished.

关键词： Chemical mechanical polishing

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Highly scalable on-axis confined cell structure for high density PRAM beyond 256Mb

Highly scalable on-axis confined cell structure for high den...

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Symposium on VLSI Technology

作者： S.L. Cho J.H. Yi Y.H. Ha B.J. Kuh C.M. Lee J.H. Park S.D. Nam H. Horii B.K. Cho K.C. Ryoo S.O. Park H.S. Kim U-In Chung J.T. Moon B.I. Ryu Process Development Team Advanced Technology Development Memory Division Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Process Development Team Process Dev. Team Samsung Electron. Co. Ltd. South Korea Memory Division Advanced Technology Development Samsung Electronics Co. LTD. Yongin-City Gyeonggi-Do Korea(ROK)

We firstly fabricated on-axis confined structure and evaluated based on 64Mb PRAM with 0.12/spl mu/m-CMOS technologies. Ge/sub 2/Sb/sub 2/Te /sub 5/ was confined within small pore, which resulted in low writing current of 0.4mA. The pore is on-axis with upper and lower contacts, which leads to good scalability of PRAM above 256Mb. The confined structure was relatively insensitive to small cell edge damage effect. The on-axis confined structure is a promising candidate for high density PRAM due to low writing current, good scalability, and insensitiveness to edge damage.

关键词： Phase change random access memory Writing Nonvolatile memory Testing Degradation Scalability Electrodes Moon Tellurium Electronics industry

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process technologies for the integration of high density phase change RAM

Process technologies for the integration of high density pha...

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IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： G.T. Jeong Y.N. Hwang S.H. Lee S.Y. Lee K.C. Ryoo J.H. Park Y.J. Song S.J. Ahn C.W. Jeong Y.-T. Kim H. Horii Y.H. Ha G.H. Koh H.S. Jeong Kinam Kim Advanced Technology Development Team Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Advanced Technology Development Team CAE Team Memory Division Samsung Electronics Company Limited Yongin si Gyeonggi South Korea CAE Team Memory Division Process Development Team Memory Division Samsung Electronics Co. Ltd. Giheung-Eup Yongin-City Gyeonggi-Do Korea

Phase change RAM (PRAM) is a promising memory that can solve the problems of conventional memory - scalability, write/read speed and reliability. The process technologies for the integration of high density PRAM are reviewed. The most important challenge of PRAM is the reduction of writing current. Various approaches to reduce the writing current are reviewed and other key factors for the high density PRAM are discussed.

关键词： Phase change random access memory Costs Writing Random access memory Scalability Flash memory Read-write memory Nonvolatile memory Redundancy Computer aided engineering

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Sub-1.2V operational, 0.15/spl mu/m/12F/sup 2/ cell FRAM technologies for next generation SoC applications

Sub-1.2V operational, 0.15/spl mu/m/12F/sup 2/ cell FRAM tec...

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Symposium on VLSI Technology

作者： Y.M. Kang J.H. Kim H.J. Joo S.K. Kang H.S. Rhie J.H. Park D.Y. Choi S.G. Oh B.J. Koo S.Y. Lee H.S. Jeong Kinam Kim Advanced Technology Development Team Semiconductor Research and Development Center Memory Division Samsung Electronics Company Limited Yongin si Gyeonggi South Korea

We have successfully demonstrated a 0.15/spl mu/m/12F/sup 2/ (0.27/spl mu/m/sup 2/) cell ITIC, COB FRAM. The key technologies for the achievement of the world smallest FRAM cell are newly developed 200nm thick ferroelectric capacitor stack technology and novel one-mask capacitor etching technology. Integration induced hydrogen damage was minimized by a new Al/sub 2/O/sub 3/ barrier processed at elevated temperature. The fully processed experimental 64k bit array of the 0.27/spl mu/m/sup 2/ FRAM cell shows a sensing window of 260mV at 1.2V. The minimum operation voltage was 0.9V. The cell size and operating voltage meet the requirements for embedded applications.

关键词： Random access memory Ferroelectric films Nonvolatile memory Capacitors Etching Electrodes Degradation Low voltage Ferroelectric materials Polarization

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Novel transition layer engineered Si nanocrystal flash memory with MHSOS structure featuring large V/sub th/ window and fast P/E speed

Novel transition layer engineered Si nanocrystal flash memor...

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International Electron Devices Meeting (IEDM)

作者： Kyong-Hee Joo Xiofeng Wang Jeong Hee Han Seung-Hyun Lim Seung-Jae Baik Yong-Won Cha Jin Wook Lee In-Seok Yeo Young-Kwan Cha In Kyeong Yoo U-In Chung Joo Tae Moon Byung-Il Ryu Process Development Team Memory DivisionSemiconductor Business Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Samsung Advanced Institute of Science and Technology Suwon South Korea

In this work, we propose a MHSOS (metal gate/high-k/SRO(silicon-rich oxide)/SiO 2 /Si) structure showing large memory window (> 4V) with fast P/E speed (plusmn18 V, 200 mus). The erase speed is featuring faster than that of Si 3 N 4 and has a retention time of 10 years for 10 % charge loss. These excellent properties were obtained through the modification of the transition layer between Si-NC and SiO 2 matrix in an SRO medium, as well as tunneling/blocking dielectric material optimization

关键词： Nanocrystals Flash memory MOSFETs Moon Tunneling Dielectric materials Nonvolatile memory Microstructure Silicon Annealing

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The texture effect on diffusion barrier property of TiN films between copper and Si wafer

The texture effect on diffusion barrier property of TiN film...

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14th International Conference on Textures of Materials, ICOTOM 14

作者： Sung, Dong Young Kim, Insoo Lee, Min Gu Park, No-Jin Yang, Beelyong Yang, Jun Mo Ko, Jung Kyu School of Advanced Materials and Systems Engineering Kumoh National Institute of Technology Kumi Kyung Buk 730-701 Korea Republic of National NanoFab Center 373-1 Guseong-dong Yuseong-gu Daejeon 305-701 Korea Republic of Memory Research and Development Division Hynix Semiconductor Inc. San 136-1 Ami-ri Bubal-eub Ichon-si Kyoungki-do 467-701 Korea Republic of

ISBN: (纸本)087849975X

TiN thin films are widely used as a coating material due to their good mechanical and conductivity properties, high thermal properties, strong erosion and corrosion resistance. Also TiN has been used in Si devices as a diffusion barrier material for Al and Cu-based metallization. The uniform and dense structure of thin films is influenced by the texture of films. It was good to have uniform and dense structure and bad to have an open columnar structure in TiN thin films. Therefore, the property of diffusion barrier of the TiN films in semiconductor also is related to the texture and microstructure of TiN coated layer. In this study, the relationship between the texture and microstructure and the best diffusion barrier propertiy of TiN coated films (by PVD and MOCVD) on semiconductor devices (Cu/TiN/SiO2/Si layer) were investigated under different processing conditions and textures. The property of diffusion barrier for Cu of physical vapor deposited TiN thin films is better than that of metal organic chemical vapor deposited TiN thin films. Also the property of diffusion barrier for Cu of (111) textured TiN thin films is better than that of (200) textured TiN thin films.

关键词： Thin films

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