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检索条件"机构=Advanced Memory Process Development Center Memory Division"

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Structural and magnetic properties of La/sub 1-x/Sr/sub x/CoO/sub 3/

Structural and magnetic properties of La/sub 1-x/Sr/sub x/Co...

引用

International Conference on Magnetics (INTERMAG)

作者： K.K. Yu J.S. Park H.R. Bae J.Y. Kim Y.P. Lee Y.S. Lee J.H. Kang Quantum Photonic Science Research Center and Department of Physics Hanyang University Seoul South Korea Division of Information Communication and Computer Engineering Hanbat National University Daejeon South Korea Process Development Team Memory Division Samsung Electronics Company Limited Yongin si South Korea

The structural and magnetic properties of the polycrystalline La/sub 1-x/Sr/sub x/CoO/sub 3/ sample synthesized by solid-state reaction were investigated. X-ray diffraction was used to study the structural properties of the sample. The ferromagnetic transition temperature (T/sub C/) and temperature dependence magnetization were determined using ac susceptibility measurement and superconducting quantum interference device (SQUID) magnetometer, respectively. High resolution neutron diffraction experiment was also carried out for the sample at different temperatures.

关键词： Magnetic properties X-ray diffraction Superconducting transition temperature Temperature dependence SQUIDs Strontium Solid state circuits Magnetization Magnetic susceptibility Superconducting devices

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Fully logic compatible (1.6V Vcc, 2 additional FRAM masks) highly reliable sub 10F2 embedded FRAM with advanced direct via technology and robust 100 nm thick MOCVD PZT technology

Fully logic compatible (1.6V Vcc, 2 additional FRAM masks) h...

引用

International Electron Devices Meeting (IEDM)

作者： J.H. Park H.J. Joo S.K. Kang Y.M. Kang H.S. Rhie B.J. Koo S.Y. Lee B.J. Bae J.E. Lim H.S. Jeong Kinam Kim Advanced Technology Development Process Development Team Memory Division Samsung Electronics Company Limited Yongin si Kyunggi South Korea Semiconductor Research and Development Center Memory Division Samsung Electronics Company Limited Yongin si Kyunggi South Korea

We newly developed a highly reliable 100 nm thick MOCVD PZT technology and a novel direct cell via technology applicable to fully logic compatible sub 10F/sup 2/ cell embedded FRAM. A 2Pr value of 40 uC/cm/sup 2/ at 1.6V was obtained on our one-mask etched new PTO seeded 100 nm thick MOCVD PZT capacitor. Capacitor degradation that could occur upon a direct application of metal on capacitor through direct via was completely prevented by combining a novel TiN-plug scheme and a diffusion barrier metal technology, which greatly improves the interface properties between top electrode and PZT. Finally, a highly reliable, 1.6V operational, sub 10F/sup 2/ cell FRAM has been successfully embedded into experimental 0.18 /spl mu/m logic with only two additional FRAM masks by successfully implementing the above two key technologies.

关键词： Random access memory Ferroelectric films Nonvolatile memory Logic Robustness MOCVD Capacitors Etching Degradation Electrodes

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Fully logic compatible (1.6V Vcc, 2 additional FRAM masks) highly reliable sub 10F2 embedded FRAM with advanced direct via technology and robust 100 nm thick MOCVD PZT technology

Fully logic compatible (1.6V Vcc, 2 additional FRAM masks) h...

引用

IEEE International Electron Devices Meeting, 2004 IEDM

作者： Park, J.H. Joo, H.J. Kang, S.K. Kang, Y.M. Rhie, H.S. Koo, B.J. Lee, S.Y. Bae, B.J. Lim, J.E. Jeong, H.S. Kim, Kinam Process Development Team Memory Division Samsung Electronics Co. Ltd. San #24 Nongseo-Li Kiheung-Eup Yongin-Si Kyungki-Do Korea Republic of Semiconductor R and D Center Memory Division Samsung Electronics Co. Ltd. San #24 Nongseo-Li Kiheung-Eup Yongin-Si Kyungki-Do Korea Republic of

We newly developed a highly reliable 100 nm thick MOCVD PZT technology and a novel direct cell via technology applicable to folly logic compatible sub 10F2 cell embedded FRAM. A 2Pr value of 40 uC/cm2 at 1.6V was obtained on our one-mask etched new PTO seeded 100 nm thick MOCVD PZT capacitor. Capacitor degradation that could occur upon a direct application of metal on capacitor through direct via was completely prevented by combining a novel TiN-plug scheme and a diffusion barrier metal technology, which greatly improves the interface properties between top electrode and PZT. Finally, a highly reliable, 1.6V operational, sub 10F2 cell FRAM has been successfully embedded into experimental 0.18 um logic with only two additional FRAM masks by successfully implementing the above two key technologies. ©2004 IEEE.

关键词： Random access storage

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Highly reliable and mass-productive FRAM embedded smartcard using advanced integration technologies

Highly reliable and mass-productive FRAM embedded smartcard ...

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Symposium on VLSI Technology

作者： H.J. Joo Y.J. Song H.H. Kim S.K. Kang J.H. Park Y.M. Kang E.Y. Kang S.Y. Lee H.S. Jeong Kinam Kim Advanced Technology Development Semiconductor Research and Development Center Memory Division Samsung Electronics Company Limited Yongin si Gyeonggi South Korea

ISBN: (纸本)0780382897

We developed FRAM embedded smartcard in which FRAM replace EEPROM and SRAM to improve the read/write cycle time and endurance of data memories in smartcard. Highly reliable sensing window for FRAM embedded smartcard was achieved by advanced integration technologies such as novel capacitor technology, multi-level encapsulating barrier layer (EBL) technology, and optimal inter-metallic dielectrics (IMD) technology.

关键词： Random access memory Ferroelectric films Nonvolatile memory Capacitors CMOS technology CMOS logic circuits Hydrogen EPROM Metallization Ferroelectric materials

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Prospects of emerging new memory technologies

Prospects of emerging new memory technologies

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IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： S.Y. Lee K. Kim Advanced Technology Development Semiconductor R&D Center Memory Division Samsung Electronics Company Limited Yongin si Gyeonggi South Korea

New types of memories with potentially ideal properties are topic of growing interest. Among the candidates, Ferroelectric RAM, Phase change RAM, and Magnetic RAM appear to be most promising for commercialization. In this paper, these memories will be reviewed in respect of current technology status, technical challenges encountered and solutions for technological barriers.

关键词： Random access memory Ferroelectric films Nonvolatile memory Ferroelectric materials Phase change random access memory MIM capacitors Dielectrics Material storage Plugs Electrodes

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Large scale integration and reliability consideration of triple gate transistors

Large scale integration and reliability consideration of tri...

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IEEE International Electron Devices Meeting, 2004 IEDM

作者： Choi, Jung A. Lee, Kwon Jin, You Seung Lee, Yong Jun Lee, Soo Yong Lee, Geon Ung Lee, Seung Hwan Sun, Min Chul Kim, Dong Chan Lee, Young Mi Bae, Su Gon Yang, Jeong Hwan Maeda, Shigenobu Lee, Nae In Kang, Ho Kyu Suh, Kwang Pyuk Advanced Technology Development Team System LSI Division Samsung Electronics Co. Ltd. San 24 Nongseo-Ri Yongin-City Kyoungi-Do 449-711 Korea Republic of ASIC PE Test System LSI Division San 24 Nongseo-Ri Yongin-City Kyoungi-Do 449-711 Korea Republic of Process Development Team Memory Division San 24 Nongseo-Ri Yongin-City Kyoungi-Do 449-711 Korea Republic of

Large scale integration and reliability of Triple Gate FETs (TG-FETs) are investigated. The SRAM chip composed of TG-FETs demonstrated 20Mbits of working cells, and 45° rotated TG-FET is found to be superior from reliability perspective. Future TG-FET design is proposed, utilizing technologies including alternating phase shift mask lithography, local-interconnects and metal gate/undoped channel. © 2004 IEEE.

关键词： Gates (transistor)

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Low power logic circuit and SRAM cell applications with silicon on depletion layer CMOS (SODEL CMOS) technology

Low power logic circuit and SRAM cell applications with sili...

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Custom Integrated Circuits Conference (CICC)

作者： S. Inaba H. Nagano K. Miyano I. Mizushima Y. Okayama T. Nakauchi K. Ishimaru H. Ishiuchi SoC Research & Development Center Toshiba Corporation Semiconductor Company Yokohama JAPAN Process & Manufacturing Engineering Center Toshiba Corporation Semiconductor Company Yokohama JAPAN Mobile Memory Device Engineering Division Toshiba Corporation Semiconductor Company Yokohama JAPAN

In this paper, the AC performance of SODEL CMOS is discussed, aiming for low power CMOS applications. Propagation delay time (/spl tau/pd) in SODEL CMOS has been improved by up to 25 % in five stacked nFET inverters, and about 30% better power-delay product has been observed at same /spl tau/pd, compared to conventional (conv.) bulk CMOS. In SRAM cell applications of SODEL CMOS, a high SNM of /spl sim/95 mV was observed at Vdd = 0.6 V. Smaller bitline delay is confirmed by SPICE simulations. Latch-up immunity for /spl alpha/-particles was found to be comparable to conv. bulk CMOS. Therefore, SODEL CMOS technology will give us better solutions for low power SoCs.

关键词： CMOS technology CMOS logic circuits Logic circuits Random access memory Silicon CMOS process Implants CMOS memory circuits FETs SPICE

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Thermally Robust Ta-Doped Ni SALICIDE process Promising for Sub-50nm CMOSFETs

Thermally Robust Ta-Doped Ni SALICIDE Process Promising for ...

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2003 Symposium on VLSI Technology

作者： Sun, M.C. Kim, M.J. Ku, J.-H. Roh, K.J. Kim, C.S. Youn, S.P. Jung, S.-W. Choi, S. Lee, N.I. Kang, H.-K. Suh, K.P. Advanced Process Development Project System LSI Division Samsung Electronics Co. Ltd. San#24 Yongin-City Gyeonggi-Do 449-900 Korea Republic of Process Development Team Memory Division Samsung Electronics Co. Ltd. San#24 Yongin-City Gyeonggi-Do 449-900 Korea Republic of

For sub-50nm device application, Self-Aligned siLICIDE (SALICIDE) process by NiTa alloy has been developed for the first time. Use of NiTa-alloy makes nickel suicide on 50nm gate thermally-robust up to 600°C during device febrication. NiTa SALICIDE process can also achieve excellent value and distribution of sheet resistance on 30nm gate as well as low junction leakage current compared to Co SALICIDE. Furthermore, the drive current of PMOS is greatly increased. As a result, high-performance 90nm MOSFETs is successfully integrated with NiTa SALICIDE process.

关键词： MOSFET devices

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A Novel Cell Technology Using N-doped GeSbTe Films for Phase Change RAM

A Novel Cell Technology Using N-doped GeSbTe Films for Phase...

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2003 Symposium on VLSI Technology

作者： Horii, H. Yi, J.H. Park, J.H. Ha, Y.H. Baek, I.G. Park, S.O. Hwang, Y.N. Lee, S.H. Kim, Y.T. Lee, K.H. Chung, U.-In. Moon, J.T. Process Development Team Memory Division Samsung Electronics Co. Ltd. San#24 Nongseo-Ree Kiheung-Eup Yongin-Si Kyungki-Do 449-711 Korea Republic of Advanced Technology Development Team Memory Division Samsung Electronics Co. Ltd. San#24 Nongseo-Ree Kiheung-Eup Yongin-Si Kyungki-Do 449-711 Korea Republic of CAE Team Memory Division Samsung Electronics Co. Ltd. San#24 Nongseo-Ree Kiheung-Eup Yongin-Si Kyungki-Do 449-711 Korea Republic of

The Ge2Sb2Te5 (GST) thin film is well known to play a critical role in PRAM (Phase Change Random Access memory). Through device simulation, we found that highresistive GST is indispensable to minimize the writing current of PRAM. For the first time, we tried to increase the GST resistivity by doping nitrogen. Doping nitrogen to GST successfully reduced writing current. Also, the cell endurance has been enhanced with grain growth suppression effect of dopant nitrogen.

关键词： Thin films

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Ultimate Solution for Low Thermal Budget Gate Spacer and Etch Stopper to Retard Short Channel Effect in Sub-90nm Devices

Ultimate Solution for Low Thermal Budget Gate Spacer and Etc...

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2003 Symposium on VLSI Technology

作者： Yang, Jong-Ho Park, Jae-Eun Lee, Joo-Won Chu, Kang-Soo Ku, Ja-Hum Park, Moon-Han Lee, Nae-In Kang, Hee-Sung Oh, Myung-Hwan Lee, Jun-Ha Kang, Ho-Kyu Suh, Kwang-Pyuk Advanced Process Development Project System LSI Division Samsung Electronics Co. Ltd. San#24 Nongseo-Ri Yongin-City Kyunggi-Do 449-711 Korea Republic of Technology Development System LSI Division Samsung Electronics Co. Ltd. Yongin-City Kyunggi-Do Korea Republic of CAE Team Memory Division Samsung Electronics Co. Ltd. Yongin-City Kyunggi-Do Korea Republic of

For the first time, by employing low thermal budget processes of ALD SiO2 and ALD SiN as gate spacer and suicide blocking layer, the short channel effects of CMOSFETs are significantly suppressed. Using the ALD SiO: and ALD SiN processes, we achieved excellent roll-off characteristics of threshold voltage in PMOS, which results in 10% increase of drive current and 15% decrease of inverter delay time. Furthermore, gate oxide reliability and static noise margin of 6T-SRAM bit cell with ALD SiO2/SiN processes are comparable to those with conventional high temperature CVD SiO 2/SiN processes. In conclusion, ALD SiO2 and ALD SiN processes of extremely low thermal budget are successfully implemented to sub-90nm CMOSFETs.

关键词： Gates (transistor)

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