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检索条件"机构=Advanced Module Process Development"

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Numerical Study on the Influence of Polyimide Thickness and Curing Temperature on Wafer Bow in Wafer Level Packaging

Numerical Study on the Influence of Polyimide Thickness and ...

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作者： Singh, Prashant Kumar Rohlfs, Patrick Sandmann, Gunther Machani, Kashi Vishwanath Breuer, Dirk Meier, Karsten Kuechenmeister, Frank Wieland, Marcel Bock, Karlheinz Advanced Packaging Development GlobalFoundries Dresden Module One LLC & Co.KG Dresden Germany Process Integration BEOL GlobalFoundries Dresden Module One LLC & Co.KG Dresden Germany Institute of Electronic Packaging Technology Technische Universität Dresden Dresden Germany Global Reliability GlobalFoundries Dresden Module One LLC & Co.KG Dresden Germany

In wafer level packaging, polyimide and electroplated copper are dielectric and conducting materials respectively in the so-called redistribution layers. During the wafer fabrication process large amount of stress is generated in those layers due to curing shrinkage of the polyimide and the coefficient of thermal expansion mismatch of both materials to silicon which can lead to severe wafer bow after a high temperature curing. In different applications polyimide can be used either only as passivation layer over electroplated copper, or polyimide is applied before the redistribution layer and then a second polyimide layer is applied as passivation. In the current study the effect of different polyimide integrations is investigated. In-situ wafer bow measurements and finite element method studies were conducted with samples, with and without polyimide below redistribution layer, exposed to different curing temperatures to understand the change in wafer bow and copper residual stress. It is observed that wafers with polyimide before redistribution layer show higher stress relaxation in copper with decreasing curing temperature, resulting therefore in a lower wafer bow. A good agreement is achieved between the experimentally measured and the simulated wafer bow. © 2023 IMAPS-International Microelectronics and Packaging Society. All rights reserved.

关键词： Residual stresses

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Influence of Annealing on Microstructure of Electroplated Copper Trenches in Back-End-Of-Line

Influence of Annealing on Microstructure of Electroplated Co...

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IEEE International Conference on Interconnect Technology

作者： Prashant Kumar Singh Maik Müller Kashi Vishwanath Machani Dirk Breuer Michael Hecker Karsten Meier Frank Kuechenmeister Marcel Wieland Karlheinz Bock Advanced Packaging Development GlobalFoundries Dresden Module One LLC & Co.KG Dresden Germany Institute of Electronic Packaging Technology Technische Universität Dresden Dresden Germany Process Integration BEOL GlobalFoundries Dresden Module One LLC & Co.KG Dresden Germany Central Labs GlobalFoundries Dresden Module One LLC & Co.KG Dresden Germany Global Reliability GlobalFoundries Dresden Module One LLC & Co.KG Dresden Germany

Copper is widely used as an interconnect material in Back-End-of-Line (BEOL) because it has high thermal conductivity and good electromigration failure resistance. However, RF applications require a larger number of ultra-thick copper metals combined with a high metal density. Due to high CTE mismatch of the copper interconnects to silicon a high wafer bow is induced during the BEOL process steps. A main contribution for the high wafer bow is the stress induced in the wafer due to annealing process steps at elevated temperature. The current study focuses on the effect of line width and annealing temperatures on stress relaxation and microstructural evolution due to aging for one month. In addition, the effect of microstructural change is studied with the time dependent wafer bow measurement showing stress relaxation over time.

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Study of Ti/TiN bump defect formation mechanism and elimination by etch process optimization

Study of Ti/TiN bump defect formation mechanism and eliminat...

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IEEE/SEMI Conference and Workshop on advanced Semiconductor Manufacturing

作者： Li-Lan Wu Yuan-Chieh Chiu Zusing Yang Sheng-Yuan Chang Hong-Ji Lee Nan-Tzu Lian Tahone Yang Kuang-Chao Chen Chih-Yuan Lu Advanced Module Process Development Div Technology Development Center Taiwan ROC

Subtle Ti/TiN bump defects are observed after thermal annealing in the development step of a back-end-of-line (BEOL) via metallization. It disturbs the endpoint detection of a sequential tungsten (W) chemical-mechanical planarization (CMP) process and results in W residue on the surface of the wafer. SIMS analysis conducted before Ti/TiN deposition indicates the presence of high concentrations of fluorine (F) atoms that have already doped into the oxide film after the via hole plasma etching process, even in the presence of an amorphous carbon hard-mask. The doped F species could diffuse out of the surface region, and then react with as-deposited Ti/TiN to form volatile TiF 4 during high-temperature annealing. As a result, severe metallic bump-like defects are observed. In this study, we report that the formation of the metallic bump defect is correlated to both the RF bias frequency, and the RF bias power applied in the capacitive-coupled fluorocarbon plasma via feature etching.

关键词： Etching Plasmas Radio frequency Metallization Plugs

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Nano-scale scratch impact on 7nm device and its improvement by predictable CMP process conditions

Nano-scale scratch impact on 7nm device and its improvement ...

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2017 International Conference on Planarization/CMP Technology, ICPT 2017

作者： Yang, Ji Chul Penigalapati, Dinesh Kumar Lu, Wen Yin Cho, Tai Fong Snyder, Alison Koli, Dinesh CMP Process Development Team Advanced Module Engineering GLOBALFOUNDRIES 400 Stonebreak Road Extension MaltaNY12020 United States CMP Unit Process Manufacturing Team Advanced Module Engineering GLOBALFOUNDRIES 400 Stonebreak Road Extension MaltaNY12020 United States

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Asymmetric etching profile control during high aspect ratio Plasma etch

Asymmetric etching profile control during high aspect ratio ...

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IEEE/SEMI Conference and Workshop on advanced Semiconductor Manufacturing

作者： Zusing Yang Li-Ian Wu Sheng-Yuan Chang Yuan-Chieh Chiu Hong-Ji Lee Nan-Tzu Lian Tahone Yang Kuang-Chao Chen Chih-Yuan Lu Hayato Watanabe Yinhwa Cheng Takao Arase Masahito Mori Macronix International Co. Ltd. Advanced Module Process Development Div. Taiwan ROC Hitachi High-Technologies Corporation Japan Hitachi High-Technologies Taiwan Corporation Taiwan

Dependency of asymmetric etched profiles on open-ratio and pattern-size within the wafer was studied in a magnetic Very High Frequency (VHF) Plasma etching system for high aspect-ratio multiple alternating layers of silicon oxide/polysilicon (OP) etching. The etched physical features are sensitive to the overall open ratio on the wafer; the profile sidewalls became bent while the open ratio changed from 8% to 40%. In this study, the profile recovery from a method of design of experiments (DOE) and specific inductively magnetic field applied in the etching system was explored. The resulting etched profile is successfully back to normal on multi-layered OP film stack at 40% of open ratio. Even at next generation node development, the etching based on DOE also demonstrates good shape control on the etched profile which stacked with OP pairs over 3um in thickness in extremely high aspect ratio trench etching.

关键词： Etching Plasmas Three-dimensional displays Erbium Shape control Conductors Polymers

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ANYSYS Chip-Level and Wafer-Level Simulation on Semiconductor process development - Yu-Chih Chang

ANYSYS Chip-Level and Wafer-Level Simulation on Semiconducto...

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2017 Joint International Symposium on e-Manufacturing and Design Collaboration, eMDC 2017 and Semiconductor Manufacturing, ISSM 2017

作者： Chen, Chi-Min Hung, Yung-Tai Luoh, Tuung Yang, Tahone Chen, Kuang-Chao Macronix International Co. Ltd Technology Development Center Advanced Module Process Development Div. No. 19 Li-Hsin Road Science Park Hsin-chu Taiwan

ISBN: (纸本)9789869171533

Most of simulation activities implemented on semiconductor manufacturing are focus on the device characteristics, and electrical properties. Less investigation pays attention on micro-structure stress/strain calculation with finite element analysis. This investigation demonstrates the ANSYS simulation results match with real cases results. The chip-level micro-structure simulations include the metal grain size behavior influence the BEOL leakage electrical properties;different design layout causes stress concentration issue, and different collapsed behavior induced by surface tension after wet strip. The wafer-level macro-structure simulation demonstrates that different pattern density of design will affect bow height performance in whole wafer. By means of ANSYS analysis, we can achieve more experiments or DOE splits by perdition simulation instead of real wafers and experiments. Thus, we can save the cost and achieve the time-to market requirement during product development. © 2017 Taiwan Semiconductor Industry Association.

关键词： Structural design

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Reduction of Wafer Arcing during High Aspect Ratio Etching

Reduction of Wafer Arcing during High Aspect Ratio Etching

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SEMI advanced Semiconductor Manufacturing Conference

作者： Zusing Yang Min-Feng Hung Kuo-Pin Chang Chih-Yao Lin Sheng-Yuan Chang Hong-Ji Lee Nan-Tzu Lian Tahone Yang Kuang-Chao Chen Chih-Yuan Lu Advanced Module Process Development Div. Macronix International Co. Ltd. Technology Development Center Hsinchu Taiwan ROC

We present several efforts for arcing reduction during high aspect ratio etching. Strategies including pulsing etching adjustments, ex situ multi-cyclic etch approach, flush step incorporation, E-chuck voltage operati... 详细信息

ISBN: (纸本)9781509054497

关键词： Arcing issue high aspect ratio trench etch 3D NAND

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Pattern damage and slurry behavior analysis of CMP process by mechanical and fluid simulations-Yi-Sheng Cheng

Pattern damage and slurry behavior analysis of CMP process b...

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Joint e-Manufacturing and Design Collaboration Symposium, eMDC 2015 and International Symposium on Semiconductor Manufacturing, ISSM 2015

作者： Yang, Wen-Cheng Luo, Shing-Ann Huang, Yukai Hung, Yung-Tai Luoh, Tuung Yang, Lin-Wuu Yang, Tahone Chen, Kuang-Chao Macronix International Co. Ltd Technology Development Center Advanced Module Process Development Div. Science Park No. 19 Li-Hsin Road Hsin-chu Taiwan

ISBN: (纸本)9789869171519

Chemical-mechanical polishing (CMP) technique is widely applied in the semiconductor industry nowadays. The CMP working mechanism is the interaction of the chemical reaction and mechanical polishing to remove the undesired materials in the circumstance with the feeding slurry and the polishing pad. As the device scale shrink, defect and uniformity control have become the major challenge and critical issues of CMP process. Since the CMP performance strongly depends on the consumable parts with complex process parameters, it may take plenty of consumable cost and working hours to improve the processes issues. Therefore the finite element method for the CMP process simulation is adopted to improve the efficiency of CMP process tuning in recent years [1]. © 2015 Taiwan Semiconductor Industry Association.

关键词： Chemical mechanical polishing

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Dishing and erosion amount prediction according pattern density calculation algorithm in 3D design layout-Kuang-Wei Chen

Dishing and erosion amount prediction according pattern dens...

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Joint e-Manufacturing and Design Collaboration Symposium, eMDC 2015 and International Symposium on Semiconductor Manufacturing, ISSM 2015

作者： Kao, Hsiao-Feng Chou, Tung-He Wu, Syue-Ren Chen, Chun-Fu Luoh, Tuung Yang, Ling-Wuu Yang, Tahone Chen, Kuang-Chao Macronix International Co. Ltd Technology Development Center Advanced Module Process Development Div. Science Park No.19 Li-Hsin Road Hsin-chu Taiwan

ISBN: (纸本)9789869171519

Chemical Mechanical Planarization (CMP) become a mainstream process in semiconductor industry, it is a key technology to generate flat and smooth surface at several critical steps in the manufacturing processes. The planarization performance is influenced by topography characteristics, line/space width, pattern density, slurry chemistry, rotation speed, PAD type, force/pressure, etc. However, as device continuous shrink, CMP process becomes more challengeable to achieve planarization. There exist two common issues that often occur at different pattern densities and line widths are dishing and erosion, as shown in Fig. 1. In STI CMP, dishing is defined as the oxide loss relative to the level of the neighboring nitride space, and erosion refers to the nitride loss relative to the nitride level of the neighboring area. Wide trenches or open structures usually enhance the dishing issue, while dense trenches lead to more erosion. Nitride erosion exposes the underlying active devices will lead to device failure;on the other hand, oxide dishing results in poor isolation. © 2015 Taiwan Semiconductor Industry Association.

关键词： Erosion

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Dishing and erosion amount prediction according pattern density calculation algorithm in 3D design layout — Kuang-Wei Chen

Dishing and erosion amount prediction according pattern dens...

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IEEE International Symposium on Semiconductor Manufacturing

作者： Hsiao-Feng Kao Tung-He Chou Syue-Ren Wu Chun-Fu Chen Tuung Luoh Ling-Wuu Yang Tahone Yang Kuang-Chao Chen Advanced Module Process Development Div. Ltd Technology Development Center Hsin-chu R.O.C Taiwan Advanced Module Process Development Div Macronix International Co. Ltd Technology Development Center Taiwan

ISBN: (纸本)9781467383271

Chemical Mechanical Planarization (CMP) become a mainstream process in semiconductor industry, it is a key technology to generate flat and smooth surface at several critical steps in the manufacturing processes. The planarization performance is influenced by topography characteristics, line/space width, pattern density, slurry chemistry, rotation speed, PAD type, force/pressure, etc. However, as device continuous shrink, CMP process becomes more challengeable to achieve planarization. There exist two common issues that often occur at different pattern densities and line widths are dishing and erosion, as shown in Fig. 1. In STI CMP, dishing is defined as the oxide loss relative to the level of the neighboring nitride space, and erosion refers to the nitride loss relative to the nitride level of the neighboring area. Wide trenches or open structures usually enhance the dishing issue, while dense trenches lead to more erosion. Nitride erosion exposes the underlying active devices will lead to device failure; on the other hand, oxide dishing results in poor isolation.

关键词： Prediction algorithms Layout Scanning electron microscopy Algorithm design and analysis Mathematical model Three-dimensional displays Planarization

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