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检索条件"机构=Advanced Module Process Development"

共 41 条记录，以下是11-20 订阅

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APF hard mask distortion improvement for high aspect ratio patterning

APF hard mask distortion improvement for high aspect ratio p...

引用

China Semiconductor Technology International Conference (CSTIC)

作者： Bing-Lung Yu YuKai Huang Shing-Ann Luo Yi-Sheng Cheng Yung-Tai Hung Tuung Luoh Lin-Wuu Yang Tahone Yang Kuang-Chao Chen Advanced Module Process Development Technology Development Center Hsin-chu Taiwan R. O. C

The goal of this research is to improve bending issue and etch durability of amorphous carbon hard mask film (APF). The design of experiments (DoE) employed variable conditions of the spacing, RF power, precursors flow (C 3 H 6 or C 2 H 2 ) and temperature. High Young's modulus and high sp 3 /sp 2 bonding ratio can increase the etching resistance, and strengthen the high aspect ratio patterning structures.

关键词： Radio frequency Stress Bonding Standards Irrigation

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Slurry selectivity to local thickness variations control in advanced Cu CMP process

Slurry selectivity to local thickness variations control in ...

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China Semiconductor Technology International Conference (CSTIC)

作者： Kuang-Wei Chen Tung-He Chou Syue-Ren Wu Chun-Fu Chen Yung-Tai Hung Tuung Luoh Ling-Wuu Yang Tahone Yang Kuang-Chao Chen Advanced Module Process Development Div Technology Development Center Hsin-chu Taiwan R.O.C

ISBN: (纸本)9781479972425

Color abnormal phenomenon in post Cu chemical mechanical planarization (CMP) is found in 3X nm flash memory. TEM cross-section shows that there is no Cu residue but has localized thickness variation. This color abnormal phenomenon cannot be eliminated with subsequently Cu and barrier polishing. According to experimental results, the non-uniform inhibitor distribution of Cu slurry issue will enhance the localized Cu dishing profile and lead to thickness variations after barrier polishing. This phenomenon is found especially at high selectivity Cu slurry in advanced Cu CMP process. Color abnormal issue is resolved by implementing the slurry with lower corrosion inhibitor concentration. Although it may have slightly dishing issue after Cu polishing, it can be optimized by subsequent barrier polishing process.

关键词： Slurries process control

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Pattern damage and slurry behavior analysis of CMP process by mechanical and fluid simulations-Yi-Sheng Cheng

Pattern damage and slurry behavior analysis of CMP process b...

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IEEE International Symposium on Semiconductor Manufacturing

作者： Wen-Cheng Yang Shing-Ann Luo YuKai Huang Yung-Tai Hung Tuung Luoh Lin-Wuu Yang Tahone Yang Kuang-Chao Chen Advanced Module Process Development Div. Technology Development Center Hsin-chu Taiwan R. O. C.

ISBN: (纸本)9781467383271

Chemical-mechanical polishing (CMP) technique is widely applied in the semiconductor industry nowadays. The CMP working mechanism is the interaction of the chemical reaction and mechanical polishing to remove the undesired materials in the circumstance with the feeding slurry and the polishing pad. As the device scale shrink, defect and uniformity control have become the major challenge and critical issues of CMP process. Since the CMP performance strongly depends on the consumable parts with complex process parameters, it may take plenty of consumable cost and working hours to improve the processes issues. Therefore the finite element method for the CMP process simulation is adopted to improve the efficiency of CMP process tuning in recent years [1].

关键词： Slurries Semiconductor device modeling Finite element analysis Stress Mathematical model Predictive models Fluids

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Influences of etcher chamber condition on critical-dimension shifts in advanced floating gate etching process

Influences of etcher chamber condition on critical-dimension...

引用

IEEE/SEMI Conference and Workshop on advanced Semiconductor Manufacturing

作者： Sheng-Yuan Chang Yu-Chung Chen An Chyi Wei Hong-Ji Lee Nan-Tzu Lian Tahone Yang Kuang-Chao Chen Chih-Yuan Lu Technology Development Center Advanced Module Process Development Division Macronix International Company Limited Hsinchu Taiwan

The authors investigated the correlation between variation of post-etch critical dimension (ECD) and etcher chamber condition during floating gate etching process. This paper presents the significantly effective method of utilizing the SF 6 /O 2 -based very long plasma-chamber cleaning or the novel Transformer coupled plasma (TCP) window temperature design not only achieves a stable gate CD (CD variation

关键词： Etching Cleaning Nonvolatile memory Logic gates Plasma temperature Polymers

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A self-aligned double patterning technology using TiN as the sidewall spacer

A self-aligned double patterning technology using TiN as the...

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IEEE/SEMI Conference and Workshop on advanced Semiconductor Manufacturing

作者： Yuan-Chieh Chiu Shu-Sheng Yu Fang-Hao Hsu Hong-Ji Lee Nan-Tzu Lian Tahone Yang Kuang-Chao Chen Chih-Yuan Lu Technology Development Center Advanced Module Process Development Division Macronix International Company Limited Hsinchu Taiwan

The TiN was conventionally used as barrier layers for both tungsten plug and AlCu metal lines. This paper reveals a novel back end of line (BEOL) self-aligned double patterning (SADP) technology, which applied TiN as a spacer material. The relative processes are introduced and discussed in detail. The new SADP approach was further applied for Cu damascene structure constructions in the advanced non-volatile memory (NVM).

关键词： Tin Silicon compounds Materials Plasmas Lithography Flash memory

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advanced floating gate CD uniformity control in the 75nm node NOR flash memory

Advanced floating gate CD uniformity control in the 75nm nod...

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IEEE/SEMI Conference and Workshop on advanced Semiconductor Manufacturing

This paper describes the advanced control technology of critical dimension uniformity (CDU) by flash gate stack etch process. We have investigated the effective way of utilizing Tri-layer approach, which not only reduces the influence of topology step-height but also improves the range of ECD within die from 17.6nm to 4.9nm. Moreover, the influence of Etcher design on ECD variation becomes larger as the cell transistor size becomes smaller. The etch chamber effect is minimized by developing CF 4 /CHF 3 /N 2 plasma at 15mTorr pressure that provides better ECD uniformity within wafer.

关键词： Plasmas Logic gates Etching Polymers Flash memory Chemistry

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Post etch killer defect characterization and reduction in a self-aligned double patterning technology

Post etch killer defect characterization and reduction in a ...

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IEEE/SEMI Conference and Workshop on advanced Semiconductor Manufacturing

作者： Hong-Ji Lee Sun-Yi Lin I-Ting Lin Kuo-Liang Wei Sheng-Yuan Chang Nan-Tzu Lian Tahone Yang Kuang-Chao Chen Chih-Yuan Lu Technology Development Center Advanced Module Process Development Division Macronix International Company Limited Hsinchu Taiwan

This paper identifies post etch killer defects, e.g., core bridging, small particle and tiny bridging, and investigates the possible solutions in a SADP module. Among the killer defect adders, core bridging and small particle are commonly observed after the oxide core removal by BOE. Core bridging adder is a carbon-containing polymeric by-product during nitride spacer open; by introducing additional diluted HF (DHF) treatment could effectively eliminate such bridging adder. Small particle adder is found to peel from the poly-Si hard mask-1 (HM1) damaged location, where is eroded during the wafer backside cleaning. It is useful for suppressing the formation of small particle by skipping the wafer backside cleaning process. Tiny bridging adder is block of etched poly-Si HM1 causing short between lines. One possibility of blocked etch adder creating is the fine micromasking formed on the opening of BARC during poly-Si HM1 etching. The effective suppression of tiny bridging adder is using high energetic F-/O-radicals to break through the micromasking in the poly-Si HM1 patterning. The reductions of above killer defects successfully boost up the sorting yield in our 45 nm charge-trapping flash memory.

关键词： Adders Etching Plasmas Cleaning Flash memory Inspection Polymers

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Yield enhancement using source/drain BF2+ implant process optimization

Yield enhancement using source/drain BF2+ implant process op...

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IEEE/SEMI Conference and Workshop on advanced Semiconductor Manufacturing

作者： Tuung Luoh Sheng-Hui Hsieh Chen-Ling Lee Hong Ji Lee Kuo-Liang Wei Chin-Ta Su Ling-Wu Yang Tahone Yang Kuang-Chao Chen Chih-Yuan Lu Technology Development Center Advanced Module Process Development Division Macronix International Company Limited Hsinchu Taiwan

This investigation employs an optimized method to alleviate defects occurring at BF 2 + implanted source/drain areas, some white spots defects found at scribes lines after BPSG (boron and phosphorus doped silicon glass) anneal. The results of physical failure analysis indicate the white spot defects are relative to outgassed fluorine that can't be released out during BPSG thermal annealing. Various approaches which includes changing the stress of post cap layer, lowering down the BF 2 + implant doping concentration, and optimizing the ramp-up speed of post-annealing are all able to alleviate the generation of white spot defects. The optimized process with an additional RTP (rapid thermal annealing) right after BF 2 + implantation delivers 7% yield improvement.

关键词： Implants Annealing Films Delamination Doping Furnaces Silicon

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Robust shallow trench isolation technique used for 75nm nor flash memory

Robust shallow trench isolation technique used for 75nm nor ...

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IEEE/SEMI Conference and Workshop on advanced Semiconductor Manufacturing

作者： Jeng-Hwa Liao Kuo-Liang Wei Hong-Ji Lee Chun-Min Cheng Chun-Ling Chiang Jung-Yu Hsieh Ling-Wu Yang Tahone Yang Kuang-Chao Chen Chih-Yuan Lu Technology Development Center Advanced Module Process Development Division Macronix International Company Limited Hsinchu Taiwan

We have developed a new Self-aligned poly (SAP) process to improve the tunnel oxide integrity by optimizing the shallow trench isolation (STI) corner rounding profile and reducing the local oxide thinning effect. It is found that double in-situ steam generation (ISSG) liner oxides can effectively improve the STI corner rounding. As for the local oxide thinning effect, the composite pad dielectrics (C-Pad) composed of SiO 2 /poly-Si are good to prevent local thinning of tunnel oxide at STI corner. Moreover, using ISSG tunnel oxide can further reduce the local oxide thinning effect. Excellent breakdown characteristics of tunnel oxide by optimizing the key technologies have been verified in this work.

关键词： Furnaces Oxidation Electric breakdown Silicon compounds Reliability Flash memory Dielectrics

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Reduction of shorts between word lines on charge-trapping flash cell in a self-aligned double patterning technology

Reduction of shorts between word lines on charge-trapping fl...

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IEEE/SEMI Conference and Workshop on advanced Semiconductor Manufacturing

作者： Hong-Ji Lee Kuo-Liang Wei Nan-Tzu Lian Tahone Yang Kuang-Chao Chen Chih-Yuan Lu Technology Development Center Advanced Module Process Development Division Macronix International Company Limited Hsinchu Taiwan

This paper presents a unique gate structure for reducing shorts between word lines on charge-trapping flash cell memory. In the early stage of developing sub-45 nm half-pitch word line by a self-aligned double patterning (SADP) technology, the cell array suffered from abnormal intrinsic word line-to-word line shorts, ca. 96.3% of the bridge rate on the 72 Mb cell memory, due to the formation of polysilicon residues called stringers. The increase of polysilicon over-etching to eliminate stringers involves a trade-off between the removal efficiency of stringers and the feature size maintenance. Hence, a novel bottle-shaped gate profile was tailor-made and studied. As a result, the bridge rates are dramatically suppressed to 0%~10% on the low-density flash cells and ca. 22% in average on the high-density 512 Mb flash cell memory. The novel bottle-shaped gate structure is successfully implemented in advanced charge-trapping flash memory development.

关键词： Logic gates Bridges Flash memory Arrays Etching Films Resists

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