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International Journal of Plasma Science and Engineering 2008年第1期2008卷 1-5页

作者： Lee, Hong-Ji Hung, Che-Lun Leng, Chia-Hao Lian, Nan-Tzu Young, Ling-Wu Yang, Tahone Chen, Kuang-Chao Lu, Chih-Yuan Advanced Module Process Development Division Technology Development Center Macronix International Company Ltd. Li-Hsin Road Hsinchu 300 Taiwan

This paper identifies the defect adders, for example, post hard-mask etch residue, post metal etch residue, and blocked etch metal island and investigates the removal characteristics of these defects within the oxide-masked Al etching process sequence. Post hard-mask etch residue containing C atom is related to the hardening of photoresist after the conventional post-RIE ashing at 275C. An in situ O2 -based plasma ashing on RIE etcher was developed to prevent the photoresist hardening from the high-ashing temperature;followed wet stripping could successfully eliminate such hardened polymeric residue. Post metal etch residue was caused from the attack of the Al sidewall by Cl atoms, and too much CHF3 addition in the Al main etch step passivated the surface of Al resulting in poor capability to remove the Al-containing residue. The lower addition of CHF3 in the Al main etch step would benefit from the residue removal. One possibility of blocked etch metal island creating was due to the micromasking formed on the opening of TiN during the hard-mask patterning. We report that an additional TiN surface pretreatment with the Ar/CHF3 /N2 plasmas could reduce the impact of the micromasking residues on blocked metal etch.

关键词： Photoresists

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Global uniformity optimization and its impact on the distribution of physical and electrical properties of Cu damascene metal lines

Global uniformity optimization and its impact on the distrib...

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22nd Annual advanced Metallization Conference, AMC 2005

作者： Kwak, B. Leo Sun, Sey-Shing Falk, Cary Burke, Peter Advanced Process Module Development LSI Logic Inc. Gresham OR 97030 United States

To counter the line resistance variations across a wafer, the deposition profile the ECD (Electrochemical Deposition) Cu was optimized. This optimisation consisted of assimilating the profile of Cu-CMP polishing rate so that the clearing of the Cu would be more uniform across the wafer, leading therefore, to more uniform erosion characteristics and physical line dimensions across a wafer. The physical and electrical results suggest that this is a viable methodology to counter the collective effects of incoming center-to-edge process biases. © 2006 Materials Research Society.

关键词： Global optimization

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Suppression of stress induced failures in Cn/low-k interconnects

Suppression of stress induced failures in Cn/low-k interconn...

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22nd Annual advanced Metallization Conference, AMC 2005

作者： Sun, Sey-Shing Kwak, B. Leo Burke, Peter Hall, Gavin D. R. Bhatt, Hemanshu Allman, Derryl LSI Logic Inc. Advanced Process Module Development and Process Integration 23400 NE Glisan Street Gresham OR 97030 United States

Barrier metal deposition and post annealing steps were investigated using LSI's newly developed stress induced voiding (SIV) test vehicle to understand their impact on SIV failures in Cu-low k interconnect. SIV fail rate vs. circuit geometry relationship was found to vary with the level of wide metal. In addition, the impact of process conditions on SIV fail rate is significant only in structures with wide metal at a lower level. Of all process parameters investigated, high temperature annealing after via/trench etch and high temperature degas prior to barrier metal deposition showed the most detrimental effect in terms of SIV failures. These results indicate that Cu is most vulnerable after via opening and before barrier metal deposition. Any thermal treatment between these two steps, e.g., post etch annealing and subsequent degas, needs to be minimized to reduce SIV failure. A lower Post ECP annealing temperature provides minor improvement while hydrogen pre-clean and Ta-first tri-layer barrier metal stack yield no positive effect. © 2006 Materials Research Society.

关键词： Failure analysis

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Global uniformity optimization and its impact on the distribution of physical and electrical properties of Cu damascene metal lines

Global uniformity optimization and its impact on the distrib...

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advanced Metallization Conference 2005, AMC 2005

作者： Kwak, B. Leo Sun, Sey-Shing Falk, Cary Burke, Peter Advanced Process Module Development LSI Logic Inc. Gresham OR 97030 United States

ISBN: (纸本)1558998659

To counter the line resistance variations across a wafer, the deposition profile the ECD (Electrochemical Deposition) Cu was optimized. This optimization consisted of assimilating the profile of Cu-CMP polishing rate so that the clearing of the Cu would be more uniform across the wafer, leading therefore, to more uniform erosion characteristics and physical line dimensions across a wafer. The physical and electrical results suggest that this is a viable methodology to counter the collective effects of incoming center-to-edge process biases. © 2006 Materials Research Society.

关键词： Copper metallurgy

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Suppression of stress induced failures in Cu/Low-k interconnects

Suppression of stress induced failures in Cu/Low-k interconn...

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advanced Metallization Conference 2005, AMC 2005

ISBN: (纸本)1558998659

关键词： LSI circuits

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Plasma ash and wet clean impact to porous low-k for multilevel Cu/low-k interconnects

Plasma ash and wet clean impact to porous low-k for multilev...

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3rd International Conference on Semiconductor Technology, ISTC2004

作者： Moore, Darren Gu, S.Q. Lu, Michael Elmer, Jim Burke, Peter Catabay, Wilbur Advanced Process Module Development LSI Logic Gresham OR 97030

Various ash plasmas and clean chemistries have been screened for compatibility with organo-silica-glass (OSG) porous low-k films (k-values of 2.2) for Cu/Low-k interconnect. Fourier Transform Infrared (FTIR) spectroscopy and k value measurement have been utilized to characterize the bulk film properties. Ash chemistries and plasma bias can reduce the film thickness, suppress SiC-bonding and weaken the film's resistance to wet clean chemistry damage. The damage to porous low-k can distort the trench profiles and induce high metal line leakage. By improving the ash and clean process, we demonstrated porous low-k/Cu interconnects with good profile and low leakage.

关键词： Dielectric devices

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An overview of stress free polishing of Cu with ultra low-k(k<2.0) films

An overview of stress free polishing of Cu with ultra low-k(...

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2003 IEEE International Interconnect Technology Conference, IITC 2003

作者： Pallinti, J. Lakshminarayanan, S. Barth, W. Wright, P. Lu, M. Reder, S. Kwak, L. Catabay, W. Wang, D. Ho, F. LSI Logic Corporation Advanced Process Module Development GreshamOR United States LSI Logic Corporation Advanced Technology Development MilpitasCA United States ACM Research Corporation FremontCA United States

ISBN: (纸本)0780377974

An overview of the process performance of Stress Free Polishing technology (SFP) for copper removal at sub 90 nm nodes is presented in this paper. A brief description of the SFP process and polishing characteristics is provided along with electrical results. Dependence of post SFP copper surface quality on the roughness of the incoming films and post plating anneal conditions is also discussed. © 2003 IEEE.

关键词： Surface roughness

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An overview of stress free polishing of Cu with ultra low-k(k<2.0) films

An overview of stress free polishing of Cu with ultra low-k(...

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IEEE International Conference on Interconnect Technology

作者： J. Pallinti S. Lakshminarayanan W. Barth P. Wright M. Lu S. Reder L. Kwak W. Catabay D. Wang F. Ho Advanced Process Module Development LSI Logic Corporation Gresham OR USA Advanced Technology Development LSI Logic Corporation Milpitas CA USA

关键词： Stress Copper Rough surfaces Surface roughness Planarization Delamination Large scale integration Logic Chemical technology Etching

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Method of increasing gate nitridation and its impact on CMOS devices

Method of increasing gate nitridation and its impact on CMOS...

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International Workshop on Gate Insulator, IWGI 2003

作者： Gopinath, V.P. Hornback, V. Le, Y. Kamath, A. Duong, L. Lin, J. Mirabedini, M.R. Yeh, W.C. Advanced Device Development LSI Logic Corporation MilipitasCA95035 United States Process Module Development LSI Logic Corporation MilipitasCA95035 United States Device Characterization LSI Logic Corporation 1621 Barber Lane MilipitasCA95035 United States

ISBN: (纸本)4891140372

A process that combines shallow nitrogen implant with rapid thermal nitridation is shown to double the nitrogen content in ultra-thin oxynitrides for the same EOT. Implanted nitrogen acts as a second source of nitrogen during gate dielectric formation and amount of incorporated nitrogen is directly proportional to the implant dose. Nitridation is shown to have opposite effects on N and PMOS mobilities. PMOS mobilities show a continuous decrease with increasing gate nitrogen content. In addition, increasing nitridation leads to severe NBTI effect on PMOS devices. Therefore, a trade-off between boron penetration resistance and performance for PMOS transistors is indicated. © 2003 Japan Society of Applied Physics.

关键词： Silicon

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Method of increasing gate nitridation and its impact on CMOS devices

Method of increasing gate nitridation and its impact on CMOS...

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International Workshop on Gate Insulator (IWGI)

作者： V.P. Gopinath V. Hornback Y. Le A. Kamath L. Duong J. Lin M.R. Mirabedini W.C. Yeh Advanced Device Development LSI Logic Corporation Milpitas CA USA Process Module Development LSI Logic Corporation Milpitas CA USA

关键词： Nitrogen MOS devices Implants Threshold voltage Gate leakage Silicon Temperature control Frequency Optical devices Dielectrics

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