This paper describes a 90 nm System-on-a-chip (SoC) technology with modular quadruple gate oxides (16, 28, 50, 64 /spl Aring/) on the same chip allowing integration of optimized transistors operating at supply voltage...
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This paper describes a 90 nm System-on-a-chip (SoC) technology with modular quadruple gate oxides (16, 28, 50, 64 /spl Aring/) on the same chip allowing integration of optimized transistors operating at supply voltages of 1, 1.2, 1.8, 2.5 and 3.3 Volts for different circuit applications. The proposed modular gate oxide process with pre-gate nitrogen implant was shown to be superior to conventional grow-etch-grow approach in terms of gate leakage current, integrity and interface quality of the multiple gate oxides. A high current drive of 1020/390 /spl mu/A//spl mu/m was demonstrated for N/P channel core transistors.
This work reports the effect of nitrogen incorporation on negative bias temperature instability (NBTI) of PMOS devices with 1.4 nm equivalent oxide thickness. It is found that for these ultra-thin oxynitrides, the lin...
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This work reports the effect of nitrogen incorporation on negative bias temperature instability (NBTI) of PMOS devices with 1.4 nm equivalent oxide thickness. It is found that for these ultra-thin oxynitrides, the linear threshold voltage degrades faster with higher content of nitrogen using both constant voltage and constant field methods.
Shallow trench isolation (STI) is the predominant isolation technology for advanced integrated circuits. Dislocations are often found at STI after repeated thermal cycles. For STI integrity, it is insufficient to have...
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ISBN:
(纸本)0780374657
Shallow trench isolation (STI) is the predominant isolation technology for advanced integrated circuits. Dislocations are often found at STI after repeated thermal cycles. For STI integrity, it is insufficient to have excellent STI patterning fidelity and rounded corners, it is also critical to have minimal thermal mismatch during oxidation and dislocation-free high-temperature annealing. Single-wafer, rapid-thermal steam oxide is found to be an excellent candidate for STI liner oxide and sacrificial oxide for that it provides lower thermal budget, rounded top and bottom corners, and significant improvement in stress release, the mechanism of which is also presented.
We have demonstrated cycle time reduction, accelerated yield learning and product introduction can be achieved by single-wafer processing without a major impact on wafer production cost. The oxidation mechanism reveal...
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ISBN:
(纸本)0780374657
We have demonstrated cycle time reduction, accelerated yield learning and product introduction can be achieved by single-wafer processing without a major impact on wafer production cost. The oxidation mechanism reveal that the ISSG oxide growth is diffusion controlled. Our results indicate the reliability of ISSG oxide is considerably improved as the process temperature increases with respect to charge-to-breakdown (Q(bd)). Such enhanced reliability of the ISSG oxide maybe explained by the reduction of the dangling bonds as the oxidation temperature increases. In addition, the ISSG process improves corner rounding of STI, which results in the elimination of the crystal defects in silicon.
Shallow trench isolation (STI) is the predominant isolation technology for advanced integrated circuits. Dislocations are often found at STI after repeated thermal cycles. For STI integrity, it is insufficient to have...
详细信息
Shallow trench isolation (STI) is the predominant isolation technology for advanced integrated circuits. Dislocations are often found at STI after repeated thermal cycles. For STI integrity, it is insufficient to have excellent STI patterning fidelity and rounded corners; it is also critical to have minimal thermal mismatch during oxidation and dislocation-free high-temperature annealing. Single-wafer, rapid-thermal steam oxide is found to be an excellent candidate for STI liner oxide and sacrificial oxide in that it provides lower thermal budget, rounded top and bottom corners, and significant improvement in stress release, the mechanism of which is also presented.
A systematic approach to generate design rules and layout guidelines for damascene metal layers that enhance the robustness and manufacturability of designs is presented. The intra-die sheet resistance variation due t...
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A systematic approach to generate design rules and layout guidelines for damascene metal layers that enhance the robustness and manufacturability of designs is presented. The intra-die sheet resistance variation due to line width and pattern density effects is characterized for single and multi-level interconnects and the feature interaction distance is determined to be about 30 /spl mu/m. It is shown that the best way to minimize the sheet resistance spread is by implementing rules for the minimum and maximum space between any two features as a function of their widths.
We have demonstrated that cycle time reduction, accelerated yield learning and product introduction can be achieved by single-wafer processing without a major impact on wafer production cost. The oxidation mechanism r...
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We have demonstrated that cycle time reduction, accelerated yield learning and product introduction can be achieved by single-wafer processing without a major impact on wafer production cost. The oxidation mechanism reveals that the ISSG oxide growth is diffusion controlled. Our results indicate the reliability of ISSG oxide is considerably improved as the process temperature increases with respect to charge-to-breakdown (Q/sub bd/). Such enhanced reliability of the ISSG oxide may be explained by the reduction of the dangling bonds as the oxidation temperature increases. In addition, the ISSG process improves the corner rounding of STI, which results in the elimination of the crystal defects in silicon.
We present constant voltage (CV) time-dependent dielectric breakdown (TDDB) measurements of integrated metal-insulator-metal (MIM) capacitors with plasma-enhanced chemical vapor deposited Si/sub 3/N/sub 4/ nitride (PE...
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We present constant voltage (CV) time-dependent dielectric breakdown (TDDB) measurements of integrated metal-insulator-metal (MIM) capacitors with plasma-enhanced chemical vapor deposited Si/sub 3/N/sub 4/ nitride (PEN) dielectric. We demonstrate tight breakdown distributions for the capacitors in a full-flow Al-based integration scheme. We achieved these excellent results by design rules to reduce plasma damage, careful process control, and an appropriate treatment of process variability. These results are superior to previously published reports that showed much wider fail time distributions for similar dielectrics and integration schemes. We also demonstrate promising performance for PEN MIM capacitors in a short-flow Cu-based integration scheme. Finally, we discuss application of several possible models ("E," "/spl radic/E," and "I/E") to the data for predicting the PEN lifetime at operating conditions.
In this paper, a full discussion of the defect reduction in copper BEOL technology of a 1P/3M logic product is presented for the first time. Defectivity is inspected from AEI to CMP on various metal levels. Defectivit...
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ISBN:
(纸本)0780366786
In this paper, a full discussion of the defect reduction in copper BEOL technology of a 1P/3M logic product is presented for the first time. Defectivity is inspected from AEI to CMP on various metal levels. Defectivity is classified into non CMP-related type and CMP-related type. Most of the non-CMP type defects are foreign matter coming from the environment or from the processing residues. They can be effectively removed in a CMP step, as long as they were not trapped in the metal trench. On the other hand, the CMP-related type defects impact the consecutive process and yield significantly. Examples of the killer defects are slurry residues, corrosion, and scratching. Prevention and reduction of defects is discussed. Product yield is greatly improved after the reduction of defectivity.
As the device technology node shrinks to sub 0.18 mum, a heavier dopant such as indium (In) is required for Super-Steep-Retrograde channel (SSR) and Halo (Pocket) implant application. Because of the difficulty in remo...
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ISBN:
(纸本)0780364627
As the device technology node shrinks to sub 0.18 mum, a heavier dopant such as indium (In) is required for Super-Steep-Retrograde channel (SSR) and Halo (Pocket) implant application. Because of the difficulty in removing residual In, cross contamination of indium in the ion implanter is the main concern for a mass production machine. This paper reviews the impact of the cross contamination on the different implant layers in 0.25 mum device process flow.
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