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检索条件"机构=Advanced Module Process Development Div."

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Alternative 3D Double Side Molded SiP for 5G Communication 18

Alternative 3D Double Side Molded SiP for 5G Communication

引用

18th International Microsystems, Packaging, Assembly and Circuits Technology Conference, IMPACT 2023

作者： Yang, Shen-Yu Tong, Yu-Wen Lin, Jing-Jun Yang, Jui-Hao Peng, Chih-Hung Chan, Chao-Chieh Research & Technology Integration Center Wistron NeWeb Corporation Advanced Mfg. Process Development Div. 5 Lihsin Rd. VI Hsinchu Science Park Hsinchu300 Taiwan

ISBN: (纸本)9798350384123

The demands for radio frequency (RF) of up-coming 5G electronic applications are gradually rising, arising recently from the need of smaller and thinner package in internet of things (IoT) and electronics devices. 3D system in package (3D SiP) including double side molding and antenna in package (AiP) could meet the above requirements. Dual side surface mounting technology (SMT) and double side molding are performed in this study to achieve miniaturization of 3D SiP module. A cost-effective and alternative molding process is completed by vacuum printing encapsulation systems (VPES) instead of common transfer molding. In this study, there are two kinds of double side molding structures, conformal and compartment molding, are employed with EMI shielding. Both molding architectures adopted conductive material as a dam to ensure electrical connectivity of side wall and sputtering metal layer to acquire EMI shielding effectiveness. To verify the reliability response of the molding structure, pre-conditioning is performed. A successful double side molding structure done by VPES with PCB warpage of 0.5 0.6 mm has been achieved in this work. Moreover, the dual side molding could reach the package requirements of 5G IoT module. © 2023 IEEE.

关键词： System-in-package

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Alternative 3D Double Side Molded SiP for 5G Communication

Alternative 3D Double Side Molded SiP for 5G Communication

引用

International Microsystems, Packaging, Assembly and Circuits Technology (IMPACT)

作者： Shen-Yu Yang Yu-Wen Tong Jing-Jun Lin Jui-Hao Yang Chih-Hung Peng Chao-Chieh Chan Advanced Mfg. Process Development Div. Research & Technology Integration Center Wistron NeWeb Corporation Hsinchu 300 Taiwan

The demands for radio frequency (RF) of up-coming 5G electronic applications are gradually rising, arising recently from the need of smaller and thinner package in internet of things (IoT) and electronics devices. 3D system in package (3D SiP) including double side molding and antenna in package (AiP) could meet the above requirements. Dual side surface mounting technology (SMT) and double side molding are performed in this study to achieve miniaturization of 3D SiP module. A cost-effective and alternative molding process is completed by vacuum printing encapsulation systems (VPES) instead of common transfer molding. In this study, there are two kinds of double side molding structures, conformal and compartment molding, are employed with EMI shielding. Both molding architectures adopted conductive material as a dam to ensure electrical connectivity of side wall and sputtering metal layer to acquire EMI shielding effectiveness. To verify the reliability response of the molding structure, pre-conditioning is performed. A successful double side molding structure done by VPES with PCB warpage of 0.5 ~0.6 mm has been achieved in this work. Moreover, the dual side molding could reach the package requirements of 5G IoT module.

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Study on thermal stress behavior of mold type POL tile

Study on thermal stress behavior of mold type POL tile

引用

Annual IEEE Conference on Applied Power Electronics Conference and Exposition (APEC)

作者： Kei Murayama Kiyoko Tajima Mikiko Kobayashi Junichi Mizushima Shingo Hayashibe Kiyoshi Oi Process Development Dept. R&D Div. Shinko Electric Industries Co. Ltd. Nagano Japan Desigining Technology Dev. R&D Div. Shinko Electric Industries Co. Ltd. Nagano Japan Advanced Products Dev. R&D Div. Shinko Electric Industries Co. Ltd. Nagano Japan

The power module industry requires smaller common packages to meet the rapidly growing demand. Power Over Lay (POL) tile is a promising candidate to meet these requirements. In this report, we will discuss the behavior of mold type POL tiles under thermal stress and the challenges they face. Temperature cycling tests were performed on several POL tile Cu wiring designs and mold resin combinations. The combination of the design with Cu wiring on the entire surface of the device and the use of high-toughness molding resin was demonstrated high reliability in temperature cycles. Thermal stress analysis results using a full-scale model of mold type POL tile with this combination showed decrease in plastic strain at Cu via connection and low damage level at pad opening portion.

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Study of Ti/TiN bump defect formation mechanism and elimination by etch process optimization

Study of Ti/TiN bump defect formation mechanism and eliminat...

引用

IEEE/SEMI Conference and Workshop on advanced Semiconductor Manufacturing

作者： Li-Lan Wu Yuan-Chieh Chiu Zusing Yang Sheng-Yuan Chang Hong-Ji Lee Nan-Tzu Lian Tahone Yang Kuang-Chao Chen Chih-Yuan Lu Advanced Module Process Development Div Technology Development Center Taiwan ROC

Subtle Ti/TiN bump defects are observed after thermal annealing in the development step of a back-end-of-line (BEOL) via metallization. It disturbs the endpoint detection of a sequential tungsten (W) chemical-mechanical planarization (CMP) process and results in W residue on the surface of the wafer. SIMS analysis conducted before Ti/TiN deposition indicates the presence of high concentrations of fluorine (F) atoms that have already doped into the oxide film after the via hole plasma etching process, even in the presence of an amorphous carbon hard-mask. The doped F species could diffuse out of the surface region, and then react with as-deposited Ti/TiN to form volatile TiF 4 during high-temperature annealing. As a result, severe metallic bump-like defects are observed. In this study, we report that the formation of the metallic bump defect is correlated to both the RF bias frequency, and the RF bias power applied in the capacitive-coupled fluorocarbon plasma via feature etching.

关键词： Etching Plasmas Radio frequency Metallization Plugs

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Asymmetric etching profile control during high aspect ratio Plasma etch

Asymmetric etching profile control during high aspect ratio ...

引用

IEEE/SEMI Conference and Workshop on advanced Semiconductor Manufacturing

作者： Zusing Yang Li-Ian Wu Sheng-Yuan Chang Yuan-Chieh Chiu Hong-Ji Lee Nan-Tzu Lian Tahone Yang Kuang-Chao Chen Chih-Yuan Lu Hayato Watanabe Yinhwa Cheng Takao Arase Masahito Mori Macronix International Co. Ltd. Advanced Module Process Development Div. Taiwan ROC Hitachi High-Technologies Corporation Japan Hitachi High-Technologies Taiwan Corporation Taiwan

Dependency of asymmetric etched profiles on open-ratio and pattern-size within the wafer was studied in a magnetic Very High Frequency (VHF) Plasma etching system for high aspect-ratio multiple alternating layers of silicon oxide/polysilicon (OP) etching. The etched physical features are sensitive to the overall open ratio on the wafer; the profile sidewalls became bent while the open ratio changed from 8% to 40%. In this study, the profile recovery from a method of design of experiments (DOE) and specific inductively magnetic field applied in the etching system was explored. The resulting etched profile is successfully back to normal on multi-layered OP film stack at 40% of open ratio. Even at next generation node development, the etching based on DOE also demonstrates good shape control on the etched profile which stacked with OP pairs over 3um in thickness in extremely high aspect ratio trench etching.

关键词： Etching Plasmas Three-dimensional displays Erbium Shape control Conductors Polymers

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ANYSYS Chip-Level and Wafer-Level Simulation on Semiconductor process development - Yu-Chih Chang

ANYSYS Chip-Level and Wafer-Level Simulation on Semiconducto...

引用

2017 Joint International Symposium on e-Manufacturing and Design Collaboration, eMDC 2017 and Semiconductor Manufacturing, ISSM 2017

作者： Chen, Chi-Min Hung, Yung-Tai Luoh, Tuung Yang, Tahone Chen, Kuang-Chao Macronix International Co. Ltd Technology Development Center Advanced Module Process Development Div. No. 19 Li-Hsin Road Science Park Hsin-chu Taiwan

ISBN: (纸本)9789869171533

Most of simulation activities implemented on semiconductor manufacturing are focus on the device characteristics, and electrical properties. Less investigation pays attention on micro-structure stress/strain calculation with finite element analysis. This investigation demonstrates the ANSYS simulation results match with real cases results. The chip-level micro-structure simulations include the metal grain size behavior influence the BEOL leakage electrical properties;different design layout causes stress concentration issue, and different collapsed behavior induced by surface tension after wet strip. The wafer-level macro-structure simulation demonstrates that different pattern density of design will affect bow height performance in whole wafer. By means of ANSYS analysis, we can achieve more experiments or DOE splits by perdition simulation instead of real wafers and experiments. Thus, we can save the cost and achieve the time-to market requirement during product development. © 2017 Taiwan Semiconductor Industry Association.

关键词： Structural design

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Reduction of Wafer Arcing during High Aspect Ratio Etching

Reduction of Wafer Arcing during High Aspect Ratio Etching

引用

SEMI advanced Semiconductor Manufacturing Conference

作者： Zusing Yang Min-Feng Hung Kuo-Pin Chang Chih-Yao Lin Sheng-Yuan Chang Hong-Ji Lee Nan-Tzu Lian Tahone Yang Kuang-Chao Chen Chih-Yuan Lu Advanced Module Process Development Div. Macronix International Co. Ltd. Technology Development Center Hsinchu Taiwan ROC

We present several efforts for arcing reduction during high aspect ratio etching. Strategies including pulsing etching adjustments, ex situ multi-cyclic etch approach, flush step incorporation, E-chuck voltage operati... 详细信息

ISBN: (纸本)9781509054497

关键词： Arcing issue high aspect ratio trench etch 3D NAND

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Pattern damage and slurry behavior analysis of CMP process by mechanical and fluid simulations-Yi-Sheng Cheng

Pattern damage and slurry behavior analysis of CMP process b...

引用

Joint e-Manufacturing and Design Collaboration Symposium, eMDC 2015 and International Symposium on Semiconductor Manufacturing, ISSM 2015

作者： Yang, Wen-Cheng Luo, Shing-Ann Huang, Yukai Hung, Yung-Tai Luoh, Tuung Yang, Lin-Wuu Yang, Tahone Chen, Kuang-Chao Macronix International Co. Ltd Technology Development Center Advanced Module Process Development Div. Science Park No. 19 Li-Hsin Road Hsin-chu Taiwan

ISBN: (纸本)9789869171519

Chemical-mechanical polishing (CMP) technique is widely applied in the semiconductor industry nowadays. The CMP working mechanism is the interaction of the chemical reaction and mechanical polishing to remove the undesired materials in the circumstance with the feeding slurry and the polishing pad. As the device scale shrink, defect and uniformity control have become the major challenge and critical issues of CMP process. Since the CMP performance strongly depends on the consumable parts with complex process parameters, it may take plenty of consumable cost and working hours to improve the processes issues. Therefore the finite element method for the CMP process simulation is adopted to improve the efficiency of CMP process tuning in recent years [1]. © 2015 Taiwan Semiconductor Industry Association.

关键词： Chemical mechanical polishing

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Dishing and erosion amount prediction according pattern density calculation algorithm in 3D design layout-Kuang-Wei Chen

Dishing and erosion amount prediction according pattern dens...

引用

Joint e-Manufacturing and Design Collaboration Symposium, eMDC 2015 and International Symposium on Semiconductor Manufacturing, ISSM 2015

作者： Kao, Hsiao-Feng Chou, Tung-He Wu, Syue-Ren Chen, Chun-Fu Luoh, Tuung Yang, Ling-Wuu Yang, Tahone Chen, Kuang-Chao Macronix International Co. Ltd Technology Development Center Advanced Module Process Development Div. Science Park No.19 Li-Hsin Road Hsin-chu Taiwan

ISBN: (纸本)9789869171519

Chemical Mechanical Planarization (CMP) become a mainstream process in semiconductor industry, it is a key technology to generate flat and smooth surface at several critical steps in the manufacturing processes. The planarization performance is influenced by topography characteristics, line/space width, pattern density, slurry chemistry, rotation speed, PAD type, force/pressure, etc. However, as device continuous shrink, CMP process becomes more challengeable to achieve planarization. There exist two common issues that often occur at different pattern densities and line widths are dishing and erosion, as shown in Fig. 1. In STI CMP, dishing is defined as the oxide loss relative to the level of the neighboring nitride space, and erosion refers to the nitride loss relative to the nitride level of the neighboring area. Wide trenches or open structures usually enhance the dishing issue, while dense trenches lead to more erosion. Nitride erosion exposes the underlying active devices will lead to device failure;on the other hand, oxide dishing results in poor isolation. © 2015 Taiwan Semiconductor Industry Association.

关键词： Erosion

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Dishing and erosion amount prediction according pattern density calculation algorithm in 3D design layout — Kuang-Wei Chen

Dishing and erosion amount prediction according pattern dens...

引用

IEEE International Symposium on Semiconductor Manufacturing

作者： Hsiao-Feng Kao Tung-He Chou Syue-Ren Wu Chun-Fu Chen Tuung Luoh Ling-Wuu Yang Tahone Yang Kuang-Chao Chen Advanced Module Process Development Div. Ltd Technology Development Center Hsin-chu R.O.C Taiwan Advanced Module Process Development Div Macronix International Co. Ltd Technology Development Center Taiwan

ISBN: (纸本)9781467383271

Chemical Mechanical Planarization (CMP) become a mainstream process in semiconductor industry, it is a key technology to generate flat and smooth surface at several critical steps in the manufacturing processes. The planarization performance is influenced by topography characteristics, line/space width, pattern density, slurry chemistry, rotation speed, PAD type, force/pressure, etc. However, as device continuous shrink, CMP process becomes more challengeable to achieve planarization. There exist two common issues that often occur at different pattern densities and line widths are dishing and erosion, as shown in Fig. 1. In STI CMP, dishing is defined as the oxide loss relative to the level of the neighboring nitride space, and erosion refers to the nitride loss relative to the nitride level of the neighboring area. Wide trenches or open structures usually enhance the dishing issue, while dense trenches lead to more erosion. Nitride erosion exposes the underlying active devices will lead to device failure; on the other hand, oxide dishing results in poor isolation.

关键词： Prediction algorithms Layout Scanning electron microscopy Algorithm design and analysis Mathematical model Three-dimensional displays Planarization

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