Fully reliable lean-free stacked capacitor, with the meshes of the supporter made of Si3N4, has been successfully developed on 80nm COB DRAM application. This novel process terminates persistent problems caused by mec...
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A manufacturable Cu/low-k multilevel interconnects have been integrated using HSQ-via-fill dual damascene process for 65nm node as stated in K.-W. Lee et al. (2003). By introducing non-porous type SiOC film (k=2.7) wi...
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A manufacturable Cu/low-k multilevel interconnects have been integrated using HSQ-via-fill dual damascene process for 65nm node as stated in K.-W. Lee et al. (2003). By introducing non-porous type SiOC film (k=2.7) without trench etch stopper and capping oxide, we obtained the effective k (keff) less than 3.0 for 65nm design rule. Simple and reliable process was achieved by improved unit process technologies such as damage-free capping oxide, abrasive free low-k direct polishing, advanced ionized PVD (AiPVD) barrier metal and bi-layer dielectric barriers, etc. according to K.C. Park et al. (2003).
Integration and reliability evaluation of phase-change random access memory (RAM) based on 0.24 μm-CMOS technologies were discussed. A nonvolatile RAM was integrated by incorporating a reversibly phase-changeable cha...
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Integration and reliability evaluation of phase-change random access memory (RAM) based on 0.24 μm-CMOS technologies were discussed. A nonvolatile RAM was integrated by incorporating a reversibly phase-changeable chalcogenide memory element with MOS transistor. Reliable performance on the device on hot temperature operation, endurance against repetitive phase transition were also presented.
A novel remote plasma-enhanced atomic layer deposition (RPEALD) silicon nitride technology is developed in a production-worthy tool for nitride/oxide (N/O) stack gate dielectric. Ultrathin N/O stack (EOT/spl sim/13 /s...
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ISBN:
(纸本)489114033X
A novel remote plasma-enhanced atomic layer deposition (RPEALD) silicon nitride technology is developed in a production-worthy tool for nitride/oxide (N/O) stack gate dielectric. Ultrathin N/O stack (EOT/spl sim/13 /spl Aring/) is realized with 50X gate leakage current reduction over thermal oxides. In addition to drastic gate current reduction, devices with RPEALD N/O stack and plasma-nitrided base oxide also exhibit well-behaved device performance and superior reliability characteristics (Qbd, TDDB, NBTI), very promising for sub-65 nm low power CMOS applications.
For the first time, a novel robust (square-shape cylinder type) TiN/AHO (Al 2O3-HfO2) /TiN capacitor with Co-silicide on landing cell pad suitable for both stand-alone and embedded DRAMs are successfully developed wit...
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For the first time, a novel robust (square-shape cylinder type) TiN/AHO (Al 2O3-HfO2) /TiN capacitor with Co-silicide on landing cell pad suitable for both stand-alone and embedded DRAMs are successfully developed with 88nm (pitch 176nm) feature size, which is the smallest feature size ever reported in DRAM technology, using ArF lithography for aiming 70nm stand-alone and embedded DRAM technology. The capacitor with Toxeq of 1.5nm and leakage current of less than 1fA/cell is achieved. The cell contact resistance is greatly improved by using Co-silicidation on landing cell pad and metal storage node contact plug, which results in high performance.
For the first time, a novel robust (square-shape cylinder type) TiN/AHO (Al/sub 2/O/sub 3/-HfO/sub 2/)/TiN capacitor with Co-silicide on landing cell pad suitable for both stand-alone and embedded DRAMs are successful...
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For the first time, a novel robust (square-shape cylinder type) TiN/AHO (Al/sub 2/O/sub 3/-HfO/sub 2/)/TiN capacitor with Co-silicide on landing cell pad suitable for both stand-alone and embedded DRAMs are successfully developed with 88nm (pitch 176nm) feature size, which is the smallest feature size ever reported in DRAM technology, using ArF lithography for aiming 70nm stand-alone and embedded DRAM technology. The capacitor with Toxeq of 1.5nm and leakage current of less than 1 fA/cell is achieved. The cell contact resistance is greatly improved by using Co-silicidation on landing cell pad and metal storage node contact plug, which results in high performance.
We have My integrated a 64 Kb MRAM with 0.24 um-CMOS technology. A new sensing scheme of separated half-current source is adopted for the reference bit line to increase sensing signal. To reduce cell resistance, Co sa...
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We have My integrated a 64 Kb MRAM with 0.24 um-CMOS technology. A new sensing scheme of separated half-current source is adopted for the reference bit line to increase sensing signal. To reduce cell resistance, Co salicidation process is applied to transistor formation. In key fabrication processes, the roughness of buffer layer, on which MTJ is stacked, is reduced by using Ru on TiN bottom electrode, and the magnetic disturbance is avoided by depositing TiN hard mask on MTJ in low-power and low-temperature condition. Especially, the micro-bridge of tunneling barrier due to the attachment of by-products during etching is completely eliminated by adopting 2-step MTJ etch with introducing a capping oxide layer. Consequently, MR values of > 30% are found in more than 90% chips.
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