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检索条件"机构=Advanced Module Technology Development"
88 条 记 录,以下是11-20 订阅
排序:
Research on Methods to Improve the Server Usage Efficiency
Research on Methods to Improve the Server Usage Efficiency
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China Semiconductor technology International Conference (CSTIC)
作者: Li Xiao Yue Wang Yueyu Zhang Advanced Module Technology Development Shanghai Huali Integrated Circuit Corporation China
In the OPC process, engineers use the core of the server to run the script to correct the mask. If the number of the core is set inappropriately, it will greatly increase the normalized running time of the script, cau... 详细信息
来源: 评论
Study on the Relationship between Transmittance and Polish Time
Study on the Relationship between Transmittance and Polish T...
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China Semiconductor technology International Conference (CSTIC)
作者: Wangbing Li Yu Yang Shubin Liu Xiaofeng Guo Jitao Chen Mingfei Yu Jingxun Fang Yu Zhang Advanced Module Technology Development Shanghai Huali Integrated Circuit Corporation Shanghai China
As the semiconductor devices of integrated circuits achieve higher levels of integration, the increasingly significant planarization impact of transmission ratio (TR) on chemical mechanical planarization (CMP) is beco... 详细信息
来源: 评论
Pad Physical Properties Effects on Removal Rate in a STI Ceria CMP Process
Pad Physical Properties Effects on Removal Rate in a STI Cer...
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China Semiconductor technology International Conference (CSTIC)
作者: Jitao Chen Yu Yang Xiao Luo Shubin Liu Xiaofeng Guo Wangbing Li Huize Du Wenqian Xie Mingfei Yu Jingxun Fang Yu Zhang Advanced Module Technology Development Shanghai Huali Integrated Circuit Corporation Shanghai China
As one of the main consumables of chemical mechanical polishing, pad plays an important role in providing mechanical polishing force, carrying and distributing polishing fluid and removing polishing by-products during... 详细信息
来源: 评论
Ebara Tungsten CMP Process Defect Improvement
Ebara Tungsten CMP Process Defect Improvement
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China Semiconductor technology International Conference (CSTIC)
作者: Tian Ding Cheng Tang Xiaoyan He Yefan Qu Qing Wang Hongwei Zhang Mingfei Yu Wenqian Xie Jingxun Fang Advanced Module Technology Development Shanghai Huali Integrated Circuit Corporation Shanghai China
Chemical-mechanical planarization (CMP) is mainly used in the manufacture of very large scale integrated circuits (ICs), where global and local planarization of wafers is obtained through chemical and mechanical proce... 详细信息
来源: 评论
Numerical Study on the Influence of Polyimide Thickness and Curing Temperature on Wafer Bow in Wafer Level Packaging  24
Numerical Study on the Influence of Polyimide Thickness and ...
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24th European Microelectronics and Packaging Conference, EMPC 2023
作者: Singh, Prashant Kumar Rohlfs, Patrick Sandmann, Gunther Machani, Kashi Vishwanath Breuer, Dirk Meier, Karsten Kuechenmeister, Frank Wieland, Marcel Bock, Karlheinz Advanced Packaging Development GlobalFoundries Dresden Module One LLC Co.KG Dresden Germany Institute of Electronic Packaging Technology Technische Universitat Dresden Dresden Germany
In wafer level packaging, polyimide and electroplated copper are dielectric and conducting materials respectively in the so-called redistribution layers. During the wafer fabrication process large amount of stress is ... 详细信息
来源: 评论
Numerical Study on the Influence of Polyimide Thickness and Curing Temperature on Wafer Bow in Wafer Level Packaging
Numerical Study on the Influence of Polyimide Thickness and ...
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作者: Singh, Prashant Kumar Rohlfs, Patrick Sandmann, Gunther Machani, Kashi Vishwanath Breuer, Dirk Meier, Karsten Kuechenmeister, Frank Wieland, Marcel Bock, Karlheinz Advanced Packaging Development GlobalFoundries Dresden Module One LLC & Co.KG Dresden Germany Process Integration BEOL GlobalFoundries Dresden Module One LLC & Co.KG Dresden Germany Institute of Electronic Packaging Technology Technische Universität Dresden Dresden Germany Global Reliability GlobalFoundries Dresden Module One LLC & Co.KG Dresden Germany
In wafer level packaging, polyimide and electroplated copper are dielectric and conducting materials respectively in the so-called redistribution layers. During the wafer fabrication process large amount of stress is ... 详细信息
来源: 评论
Pattern Loading Improvement for CU CMP Process
Pattern Loading Improvement for CU CMP Process
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China Semiconductor technology International Conference (CSTIC)
作者: Lei Zhang Yu Yang Jian Zhang Jingxun Fang Yu Zhang Advanced Module Technology Development Shanghai Huali Integrated Circuit Corporation Shanghai China
Chemical mechanical polishing (CMP) is becoming a widely used technology to meet the precise machining in various applications. And also, the topography of pattern wafer surface shows very serious challenges. In semic...
来源: 评论
Study on the Mechanism of CMP Induced W Seam at advanced technology Node
Study on the Mechanism of CMP Induced W Seam at Advanced Tec...
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China Semiconductor technology International Conference (CSTIC)
作者: Shaojia Zhu Yurong Que Feng Shi Mingfei Yu Jian Zhang Jingxun Fang Yu Zhang Advanced Module Technology Development Shanghai Huali Integrated Circuit Corporation Shanghai China
W seam is a common defect post WCMP at advanced technology node, which seriously affects the electrical performance of the device and the yield of the chip. The mainly suspected directions are the poor ability of the ...
来源: 评论
Numerical Study on the Influence of Polyimide Thickness and Curing Temperature on Wafer Bow in Wafer Level Packaging
Numerical Study on the Influence of Polyimide Thickness and ...
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European Microelectronics and Packaging Conference, EMPC
作者: Prashant Kumar Singh Patrick Rohlfs Gunther Sandmann Kashi Vishwanath Machani Dirk Breuer Karsten Meier Frank Kuechenmeister Marcel Wieland Karlheinz Bock Advanced Packaging Development GlobalFoundries Dresden Module One LLC & Co.KG Dresden Germany Institute of Electronic Packaging Technology Technische Universität Dresden Dresden Germany
In wafer level packaging, polyimide and electroplated copper are dielectric and conducting materials respectively in the so-called redistribution layers. During the wafer fabrication process large amount of stress is ...
来源: 评论
Influence of Annealing on Microstructure of Electroplated Copper Trenches in Back-End-Of-Line
Influence of Annealing on Microstructure of Electroplated Co...
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IEEE International Conference on Interconnect technology
作者: Prashant Kumar Singh Maik Müller Kashi Vishwanath Machani Dirk Breuer Michael Hecker Karsten Meier Frank Kuechenmeister Marcel Wieland Karlheinz Bock Advanced Packaging Development GlobalFoundries Dresden Module One LLC & Co.KG Dresden Germany Institute of Electronic Packaging Technology Technische Universität Dresden Dresden Germany Process Integration BEOL GlobalFoundries Dresden Module One LLC & Co.KG Dresden Germany Central Labs GlobalFoundries Dresden Module One LLC & Co.KG Dresden Germany Global Reliability GlobalFoundries Dresden Module One LLC & Co.KG Dresden Germany
Copper is widely used as an interconnect material in Back-End-of-Line (BEOL) because it has high thermal conductivity and good electromigration failure resistance. However, RF applications require a larger number of u...
来源: 评论