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IEEE/SEMI Conference and Workshop on advanced Semiconductor Manufacturing

作者： Li-Lan Wu Yuan-Chieh Chiu Zusing Yang Sheng-Yuan Chang Hong-Ji Lee Nan-Tzu Lian Tahone Yang Kuang-Chao Chen Chih-Yuan Lu Advanced Module Process Development Div Technology Development Center Taiwan ROC

Subtle Ti/TiN bump defects are observed after thermal annealing in the development step of a back-end-of-line (BEOL) via metallization. It disturbs the endpoint detection of a sequential tungsten (W) chemical-mechanical planarization (CMP) process and results in W residue on the surface of the wafer. SIMS analysis conducted before Ti/TiN deposition indicates the presence of high concentrations of fluorine (F) atoms that have already doped into the oxide film after the via hole plasma etching process, even in the presence of an amorphous carbon hard-mask. The doped F species could diffuse out of the surface region, and then react with as-deposited Ti/TiN to form volatile TiF 4 during high-temperature annealing. As a result, severe metallic bump-like defects are observed. In this study, we report that the formation of the metallic bump defect is correlated to both the RF bias frequency, and the RF bias power applied in the capacitive-coupled fluorocarbon plasma via feature etching.

关键词： Etching Plasmas Radio frequency Metallization Plugs

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Wafer backside cleaning for defect reduction and litho hot spots mitigation: DI: Defect inspection and reduction

Wafer backside cleaning for defect reduction and litho hot s...

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IEEE/SEMI Conference and Workshop on advanced Semiconductor Manufacturing

作者： Elango Balu Wei-Tsu Tseng David Jayez Jay Mody Keith Donegan Advanced Module Engineering (AME) GLOBALFOUNDRIES Malta NY USA Center for Complex Analysis Advanced Technology Development (ATD) GLOBALFOUNDRIES Malta NY USA

With each new advanced technology node, minimum feature sizes continue to shrink. As a result, the devices become denser and exposure tool's depth of focus decreases - making lithography one of the most crucial modules in the process flow. Hence, the elimination of hot spots triggered by problematic pattern regions based on optical simulation, by cleaning wafer backside is a critical issue that needs to be addressed to prevent significant yield degradation.

关键词： Tools Chemicals Brushes Rough surfaces Surface roughness Surface cleaning

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ANYSYS Chip-Level and Wafer-Level Simulation on Semiconductor Process development - Yu-Chih Chang

ANYSYS Chip-Level and Wafer-Level Simulation on Semiconducto...

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2017 Joint International Symposium on e-Manufacturing and Design Collaboration, eMDC 2017 and Semiconductor Manufacturing, ISSM 2017

作者： Chen, Chi-Min Hung, Yung-Tai Luoh, Tuung Yang, Tahone Chen, Kuang-Chao Macronix International Co. Ltd Technology Development Center Advanced Module Process Development Div. No. 19 Li-Hsin Road Science Park Hsin-chu Taiwan

ISBN: (纸本)9789869171533

Most of simulation activities implemented on semiconductor manufacturing are focus on the device characteristics, and electrical properties. Less investigation pays attention on micro-structure stress/strain calculation with finite element analysis. This investigation demonstrates the ANSYS simulation results match with real cases results. The chip-level micro-structure simulations include the metal grain size behavior influence the BEOL leakage electrical properties;different design layout causes stress concentration issue, and different collapsed behavior induced by surface tension after wet strip. The wafer-level macro-structure simulation demonstrates that different pattern density of design will affect bow height performance in whole wafer. By means of ANSYS analysis, we can achieve more experiments or DOE splits by perdition simulation instead of real wafers and experiments. Thus, we can save the cost and achieve the time-to market requirement during product development. © 2017 Taiwan Semiconductor Industry Association.

关键词： Structural design

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SiOC CMP developed and implemented in 7nm and beyond

SiOC CMP developed and implemented in 7nm and beyond

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China Semiconductor technology International Conference (CSTIC)

作者： Haigou Huang Taifong Chao Ja-Hyung Han Dinesh Koli Qiang Fang Advanced Module Engineering Globalfoundries Malta NY USA Advanced Technology Development GLOBALFOUNDRIES Malta NY USA

ISBN: (纸本)9781509066957

In this study, new SiOC Chemical Mechanical Planarization (CMP) process is fully developed with the characterization of the blanket wafer selectivity, SiN loss on pattern wafer, within chip SiN uniformity, and topography of CMP house and device areas using Atomic-force microscopy (AFM), Transmission electron microscopy (TEM), high resolution profiler (HRP) and KLA-Aleris. Those results of SiN within-chip uniformity show one step process (only slurry A_bulk + SiN stop) with poor process window, which cannot meet 7nm MOL integration process requirement. And two steps process (Slurry A_bulk + Slurry B_SiN stop) with promising results, good SiN within-chip uniformity (

关键词： Planarization Facsimile

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Effect of Hydrogen on Reliability with Various Deposition Temperatures of Al2O3 Gate Insulator in In-Ga-Zn-O Thin Film Transistors

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ECS Meeting Abstracts 2018年第22期MA2018-01卷

作者： Kyoungwoo Park Guk-Jin Jeon Seung Hee Lee Sang-Hee Ko Park KAIST Korea Advanced Institute of Science and Technology Module Development Team Samsung Display KAIST

To achieve the next generation displays, it is becoming increasingly important to develop backplane technology with superior characteristics such as high mobility, high stability, and high transparency. Among the several candidates for suitable backplane in high definition display, amorphous In-Ga-Zn-O (a-IGZO) oxide semiconductor TFTs have attracted much interest due to its high mobility, optical transparency, and large area uniformity. However, due to the intrinsic problem of a-IGZO TFTs caused by oxygen vacancy and hydrogen, it is hard to control of threshold voltage (Vth) and stability under various stress conditions. One of them, hydrogen is the main factor closely related to reliability. According to previous studies, hydrogen acts as positive roles by defect passivation and also play negative roles in creating new defects in a-IGZO active layer. However, incorporation and diffusion of hydrogen into the active layer is an unavoidable issue during the TFTs fabrication, and it is important to control it so that hydrogen plays a positive role. So, in this study, we conducted experiments to verify the effect of hydrogen on the reliability by modifying the Al2O3 gate insulator layer (GI) deposition process using atomic layer deposition (ALD) method. In order to verify the relationship between the hydrogen and electrical properties of a-IGZO TFTs, we fabricated top gate bottom contact (TGBC) structures and applied different GI deposition temperature (Tdep) for controlling the amount of hydrogen. [1] Al2O3 GI deposited using trimethylaluminum (TMA) and H2O precursor. Each Tdep are 200, 250, 270 and 300 degree, respectively. As a result of Al2O3 single thin film analysis using secondary ion mass spectroscopy (SIMS) method, it was confirmed that the Al2O3 thin film deposited at high Tdep has a relatively small amount of hydrogen than the Al2O3 thin film deposited at low Tdep. And then, TFT devices a, b, c, and d were fabricated using Al2O3 GI with different Tdep of 200

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Reduction of Wafer Arcing during High Aspect Ratio Etching

Reduction of Wafer Arcing during High Aspect Ratio Etching

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SEMI advanced Semiconductor Manufacturing Conference

作者： Zusing Yang Min-Feng Hung Kuo-Pin Chang Chih-Yao Lin Sheng-Yuan Chang Hong-Ji Lee Nan-Tzu Lian Tahone Yang Kuang-Chao Chen Chih-Yuan Lu Advanced Module Process Development Div. Macronix International Co. Ltd. Technology Development Center Hsinchu Taiwan ROC

We present several efforts for arcing reduction during high aspect ratio etching. Strategies including pulsing etching adjustments, ex situ multi-cyclic etch approach, flush step incorporation, E-chuck voltage operati... 详细信息

ISBN: (纸本)9781509054497

关键词： Arcing issue high aspect ratio trench etch 3D NAND

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Pattern damage and slurry behavior analysis of CMP process by mechanical and fluid simulations-Yi-Sheng Cheng

Pattern damage and slurry behavior analysis of CMP process b...

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Joint e-Manufacturing and Design Collaboration Symposium, eMDC 2015 and International Symposium on Semiconductor Manufacturing, ISSM 2015

作者： Yang, Wen-Cheng Luo, Shing-Ann Huang, Yukai Hung, Yung-Tai Luoh, Tuung Yang, Lin-Wuu Yang, Tahone Chen, Kuang-Chao Macronix International Co. Ltd Technology Development Center Advanced Module Process Development Div. Science Park No. 19 Li-Hsin Road Hsin-chu Taiwan

ISBN: (纸本)9789869171519

Chemical-mechanical polishing (CMP) technique is widely applied in the semiconductor industry nowadays. The CMP working mechanism is the interaction of the chemical reaction and mechanical polishing to remove the undesired materials in the circumstance with the feeding slurry and the polishing pad. As the device scale shrink, defect and uniformity control have become the major challenge and critical issues of CMP process. Since the CMP performance strongly depends on the consumable parts with complex process parameters, it may take plenty of consumable cost and working hours to improve the processes issues. Therefore the finite element method for the CMP process simulation is adopted to improve the efficiency of CMP process tuning in recent years [1]. © 2015 Taiwan Semiconductor Industry Association.

关键词： Chemical mechanical polishing

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Dishing and erosion amount prediction according pattern density calculation algorithm in 3D design layout-Kuang-Wei Chen

Dishing and erosion amount prediction according pattern dens...

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Joint e-Manufacturing and Design Collaboration Symposium, eMDC 2015 and International Symposium on Semiconductor Manufacturing, ISSM 2015

作者： Kao, Hsiao-Feng Chou, Tung-He Wu, Syue-Ren Chen, Chun-Fu Luoh, Tuung Yang, Ling-Wuu Yang, Tahone Chen, Kuang-Chao Macronix International Co. Ltd Technology Development Center Advanced Module Process Development Div. Science Park No.19 Li-Hsin Road Hsin-chu Taiwan

ISBN: (纸本)9789869171519

Chemical Mechanical Planarization (CMP) become a mainstream process in semiconductor industry, it is a key technology to generate flat and smooth surface at several critical steps in the manufacturing processes. The planarization performance is influenced by topography characteristics, line/space width, pattern density, slurry chemistry, rotation speed, PAD type, force/pressure, etc. However, as device continuous shrink, CMP process becomes more challengeable to achieve planarization. There exist two common issues that often occur at different pattern densities and line widths are dishing and erosion, as shown in Fig. 1. In STI CMP, dishing is defined as the oxide loss relative to the level of the neighboring nitride space, and erosion refers to the nitride loss relative to the nitride level of the neighboring area. Wide trenches or open structures usually enhance the dishing issue, while dense trenches lead to more erosion. Nitride erosion exposes the underlying active devices will lead to device failure;on the other hand, oxide dishing results in poor isolation. © 2015 Taiwan Semiconductor Industry Association.

关键词： Erosion

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Dishing and erosion amount prediction according pattern density calculation algorithm in 3D design layout — Kuang-Wei Chen

Dishing and erosion amount prediction according pattern dens...

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IEEE International Symposium on Semiconductor Manufacturing

作者： Hsiao-Feng Kao Tung-He Chou Syue-Ren Wu Chun-Fu Chen Tuung Luoh Ling-Wuu Yang Tahone Yang Kuang-Chao Chen Advanced Module Process Development Div. Ltd Technology Development Center Hsin-chu R.O.C Taiwan Advanced Module Process Development Div Macronix International Co. Ltd Technology Development Center Taiwan

ISBN: (纸本)9781467383271

Chemical Mechanical Planarization (CMP) become a mainstream process in semiconductor industry, it is a key technology to generate flat and smooth surface at several critical steps in the manufacturing processes. The planarization performance is influenced by topography characteristics, line/space width, pattern density, slurry chemistry, rotation speed, PAD type, force/pressure, etc. However, as device continuous shrink, CMP process becomes more challengeable to achieve planarization. There exist two common issues that often occur at different pattern densities and line widths are dishing and erosion, as shown in Fig. 1. In STI CMP, dishing is defined as the oxide loss relative to the level of the neighboring nitride space, and erosion refers to the nitride loss relative to the nitride level of the neighboring area. Wide trenches or open structures usually enhance the dishing issue, while dense trenches lead to more erosion. Nitride erosion exposes the underlying active devices will lead to device failure; on the other hand, oxide dishing results in poor isolation.

关键词： Prediction algorithms Layout Scanning electron microscopy Algorithm design and analysis Mathematical model Three-dimensional displays Planarization

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Slurry selectivity to local thickness variations control in advanced Cu CMP process

Slurry selectivity to local thickness variations control in ...

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China Semiconductor technology International Conference (CSTIC)

作者： Kuang-Wei Chen Tung-He Chou Syue-Ren Wu Chun-Fu Chen Yung-Tai Hung Tuung Luoh Ling-Wuu Yang Tahone Yang Kuang-Chao Chen Advanced Module Process Development Div Technology Development Center Hsin-chu Taiwan R.O.C

ISBN: (纸本)9781479972425

Color abnormal phenomenon in post Cu chemical mechanical planarization (CMP) is found in 3X nm flash memory. TEM cross-section shows that there is no Cu residue but has localized thickness variation. This color abnormal phenomenon cannot be eliminated with subsequently Cu and barrier polishing. According to experimental results, the non-uniform inhibitor distribution of Cu slurry issue will enhance the localized Cu dishing profile and lead to thickness variations after barrier polishing. This phenomenon is found especially at high selectivity Cu slurry in advanced Cu CMP process. Color abnormal issue is resolved by implementing the slurry with lower corrosion inhibitor concentration. Although it may have slightly dishing issue after Cu polishing, it can be optimized by subsequent barrier polishing process.

关键词： Slurries Process control

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