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China Semiconductor technology International Conference (CSTIC)

作者： Bing-Lung Yu YuKai Huang Shing-Ann Luo Yi-Sheng Cheng Yung-Tai Hung Tuung Luoh Lin-Wuu Yang Tahone Yang Kuang-Chao Chen Advanced Module Process Development Technology Development Center Hsin-chu Taiwan R. O. C

The goal of this research is to improve bending issue and etch durability of amorphous carbon hard mask film (APF). The design of experiments (DoE) employed variable conditions of the spacing, RF power, precursors flow (C 3 H 6 or C 2 H 2 ) and temperature. High Young's modulus and high sp 3 /sp 2 bonding ratio can increase the etching resistance, and strengthen the high aspect ratio patterning structures.

关键词： Radio frequency Stress Bonding Standards Irrigation

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Pattern damage and slurry behavior analysis of CMP process by mechanical and fluid simulations-Yi-Sheng Cheng

Pattern damage and slurry behavior analysis of CMP process b...

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IEEE International Symposium on Semiconductor Manufacturing

作者： Wen-Cheng Yang Shing-Ann Luo YuKai Huang Yung-Tai Hung Tuung Luoh Lin-Wuu Yang Tahone Yang Kuang-Chao Chen Advanced Module Process Development Div. Technology Development Center Hsin-chu Taiwan R. O. C.

ISBN: (纸本)9781467383271

Chemical-mechanical polishing (CMP) technique is widely applied in the semiconductor industry nowadays. The CMP working mechanism is the interaction of the chemical reaction and mechanical polishing to remove the undesired materials in the circumstance with the feeding slurry and the polishing pad. As the device scale shrink, defect and uniformity control have become the major challenge and critical issues of CMP process. Since the CMP performance strongly depends on the consumable parts with complex process parameters, it may take plenty of consumable cost and working hours to improve the processes issues. Therefore the finite element method for the CMP process simulation is adopted to improve the efficiency of CMP process tuning in recent years [1].

关键词： Slurries Semiconductor device modeling Finite element analysis Stress Mathematical model Predictive models Fluids

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Influences of etcher chamber condition on critical-dimension shifts in advanced floating gate etching process

Influences of etcher chamber condition on critical-dimension...

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IEEE/SEMI Conference and Workshop on advanced Semiconductor Manufacturing

作者： Sheng-Yuan Chang Yu-Chung Chen An Chyi Wei Hong-Ji Lee Nan-Tzu Lian Tahone Yang Kuang-Chao Chen Chih-Yuan Lu Technology Development Center Advanced Module Process Development Division Macronix International Company Limited Hsinchu Taiwan

The authors investigated the correlation between variation of post-etch critical dimension (ECD) and etcher chamber condition during floating gate etching process. This paper presents the significantly effective method of utilizing the SF 6 /O 2 -based very long plasma-chamber cleaning or the novel Transformer coupled plasma (TCP) window temperature design not only achieves a stable gate CD (CD variation

关键词： Etching Cleaning Nonvolatile memory Logic gates Plasma temperature Polymers

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A self-aligned double patterning technology using TiN as the sidewall spacer

A self-aligned double patterning technology using TiN as the...

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IEEE/SEMI Conference and Workshop on advanced Semiconductor Manufacturing

作者： Yuan-Chieh Chiu Shu-Sheng Yu Fang-Hao Hsu Hong-Ji Lee Nan-Tzu Lian Tahone Yang Kuang-Chao Chen Chih-Yuan Lu Technology Development Center Advanced Module Process Development Division Macronix International Company Limited Hsinchu Taiwan

The TiN was conventionally used as barrier layers for both tungsten plug and AlCu metal lines. This paper reveals a novel back end of line (BEOL) self-aligned double patterning (SADP) technology, which applied TiN as a spacer material. The relative processes are introduced and discussed in detail. The new SADP approach was further applied for Cu damascene structure constructions in the advanced non-volatile memory (NVM).

关键词： Tin Silicon compounds Materials Plasmas Lithography Flash memory

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Design, modeling, and performance evaluation of a novel dye cell for a high repetition rate dye laser

Design, modeling, and performance evaluation of a novel dye ...

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作者： Singh, Nageshwar Patel, Hemant K. Dixit, S.K. Vora, H.S. Magnetic and Superconducting Materials Section Materials Advanced Accelerator Sciences Division Raja Ramanna Centre for Advanced Technology Indore - 452013 M.P. India Cryo-engineering and Cryo-module Development Section Raja Ramanna Centre for Advanced Technology Indore - 452013 M.P. India Laser Systems Engineering Section Raja Ramanna Centre for Advanced Technology Indore - 452013 M.P. India Laser Engineering Support Division Raja Ramanna Centre for Advanced Technology Indore - 452013 M.P. India

In this paper, a new dye cell for transverse pumping was designed, modeled, and its performance in a narrow spectral width dispersive resonator, pumped by a high repetition rate copper vapor laser, was investigated. The scheme essentially involves the profiling of the cubical glass and stainless steel cylindrical surface such that convex-plano contour be present near the optical pumping region. The design is an amalgamation of straight and curved periphery to enhance the dye solution flow stabilities near the dye laser axis. A computational fluid dynamics analysis of the liquid flow through this dye cell has been carried out. The dye laser outputs such as optical average power, spectral width and wavelength stability, tuning range, pulse shape, through this new dye cell was evaluated. The dye laser average power about 30 mW was fairly steady over the observation period of more than an hour. The dye laser short-term (1 min) spectral width was within 0.824 ± 0.075 GHz, while, in a long-term, more than an hour, drifted by about 180 MHz. The dye laser wavelength in short-term fluctuates within ±0.0065 nm whereas in a long-term, more than an hour, drifted by about 0.0105 nm. The dye laser tuning range was 10 nm with a sub GHz spectral width operation. The pulse shape of the dye laser follows the pump laser pulse profile. Thus, the dye laser has demonstrated fairly long-term stability, without the use of either low expansion material or close loop control on the output. © 2012 American Institute of Physics.

关键词： Dye lasers

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Post Cu CMP cleaning process evaluation for 32nm and 22nm technology nodes

Post Cu CMP cleaning process evaluation for 32nm and 22nm te...

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IEEE/SEMI Conference and Workshop on advanced Semiconductor Manufacturing

作者： Wei-Tsu Tseng Donald Canaperi Adam Ticknor Vamsi Devarapalli Leo Tai Laertis Economikos James MacDougal Christine Bunke Matthew Angyal Jennifer Muncy Xiaomeng Chen John Zhang Qiang Fang Jianping Zheng IBM Semiconductor Research and Development Center Hopewell Junction NY USA IBM at Albany Nanotech Albany NY USA Silicon Technology Development STMicroelectronics Inc. Hopewell Junction NY USA Advanced Module Technology Development GLOBALFOUNDRIES Hopewell Junction NY USA

Optimization of post Cu CMP cleaning performance can be accomplished through dilution ratio tuning and pad rinse of clean chemicals. Excessive chemical etching as well as megasonic power can induce high Cu roughness. Generation of hollow metal and Cu dendrite defects depends not only on the clean chemistry but also the queue time between plating and anneal and between CMP and cap. AFM and XPS provide insights into the cleaning mechanism. EM and TDDB tests are the ultimate tests for the effectiveness of post Cu CMP cleaning.

关键词： Chemicals Surface cleaning Annealing Frequency modulation Metals

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Dependence of 4H-SiC Epitaxial Layer Quality on Growth Conditions with Wafer Size Corresponding to 150 mm

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MRS Online Proceedings Library 2012年第1期1433卷 59-64页

作者： Kudou, Chiaki Tamura, Kentaro Aigo, Takashi Ito, Wataru Nishio, Johji Kojima, Kazutoishi Ohno, Toshiyuki R&D Partnership for Future Power Electronics Technology (FUPET) Ibaraki Japan Device Module Development Center Panasonic Corporation Okayama Japan ROHM Co. Ltd Kyoto Japan NIPPON STEEL CORPORATION Chiba-prefecture Japan Toshiba Corporation Kawasaki Japan National Institute of Advanced Industrial Science and Technology (AIST) Ibaraki Japan Hitachi Ltd Tokyo Japan

Homoepitaxial growth on 4H-SiC Si-face substrates with sizes corresponding to 150 mm was carried out. The influence of growth conditions for uniformity and epitaxial defect density was investigated. A 150 mm size was realized by using two 76.2 mm wafers lined up in a radial direction. C/Si ratio is found to be a major parameter for controlling triangular defect density and the generation of step bunching. As a result, the surface morphology without bunched step structure and the triangular defect density with 0.5 cm−2 were obtained by decreasing C/Si ratio to 1.0 on the size corresponding to 150 mm. Under this condition, good carrier concentration and thickness uniformity of σ/mean =15.2 % and 1.7 % could be obtained.

关键词： epitaxy morphology defects

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advanced floating gate CD uniformity control in the 75nm node NOR flash memory

Advanced floating gate CD uniformity control in the 75nm nod...

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IEEE/SEMI Conference and Workshop on advanced Semiconductor Manufacturing

This paper describes the advanced control technology of critical dimension uniformity (CDU) by flash gate stack etch process. We have investigated the effective way of utilizing Tri-layer approach, which not only reduces the influence of topology step-height but also improves the range of ECD within die from 17.6nm to 4.9nm. Moreover, the influence of Etcher design on ECD variation becomes larger as the cell transistor size becomes smaller. The etch chamber effect is minimized by developing CF 4 /CHF 3 /N 2 plasma at 15mTorr pressure that provides better ECD uniformity within wafer.

关键词： Plasmas Logic gates Etching Polymers Flash memory Chemistry

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Post etch killer defect characterization and reduction in a self-aligned double patterning technology

Post etch killer defect characterization and reduction in a ...

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IEEE/SEMI Conference and Workshop on advanced Semiconductor Manufacturing

作者： Hong-Ji Lee Sun-Yi Lin I-Ting Lin Kuo-Liang Wei Sheng-Yuan Chang Nan-Tzu Lian Tahone Yang Kuang-Chao Chen Chih-Yuan Lu Technology Development Center Advanced Module Process Development Division Macronix International Company Limited Hsinchu Taiwan

This paper identifies post etch killer defects, e.g., core bridging, small particle and tiny bridging, and investigates the possible solutions in a SADP module. Among the killer defect adders, core bridging and small particle are commonly observed after the oxide core removal by BOE. Core bridging adder is a carbon-containing polymeric by-product during nitride spacer open; by introducing additional diluted HF (DHF) treatment could effectively eliminate such bridging adder. Small particle adder is found to peel from the poly-Si hard mask-1 (HM1) damaged location, where is eroded during the wafer backside cleaning. It is useful for suppressing the formation of small particle by skipping the wafer backside cleaning process. Tiny bridging adder is block of etched poly-Si HM1 causing short between lines. One possibility of blocked etch adder creating is the fine micromasking formed on the opening of BARC during poly-Si HM1 etching. The effective suppression of tiny bridging adder is using high energetic F-/O-radicals to break through the micromasking in the poly-Si HM1 patterning. The reductions of above killer defects successfully boost up the sorting yield in our 45 nm charge-trapping flash memory.

关键词： Adders Etching Plasmas Cleaning Flash memory Inspection Polymers

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Yield enhancement using source/drain BF2+ implant process optimization

Yield enhancement using source/drain BF2+ implant process op...

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IEEE/SEMI Conference and Workshop on advanced Semiconductor Manufacturing

作者： Tuung Luoh Sheng-Hui Hsieh Chen-Ling Lee Hong Ji Lee Kuo-Liang Wei Chin-Ta Su Ling-Wu Yang Tahone Yang Kuang-Chao Chen Chih-Yuan Lu Technology Development Center Advanced Module Process Development Division Macronix International Company Limited Hsinchu Taiwan

This investigation employs an optimized method to alleviate defects occurring at BF 2 + implanted source/drain areas, some white spots defects found at scribes lines after BPSG (boron and phosphorus doped silicon glass) anneal. The results of physical failure analysis indicate the white spot defects are relative to outgassed fluorine that can't be released out during BPSG thermal annealing. Various approaches which includes changing the stress of post cap layer, lowering down the BF 2 + implant doping concentration, and optimizing the ramp-up speed of post-annealing are all able to alleviate the generation of white spot defects. The optimized process with an additional RTP (rapid thermal annealing) right after BF 2 + implantation delivers 7% yield improvement.

关键词： Implants Annealing Films Delamination Doping Furnaces Silicon

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