This paper presents a unique gate structure for reducing shorts between word lines on charge-trapping flash cell memory. In the early stage of developing sub-45 nm half-pitch word line by a self-aligned double pattern...
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This paper presents a unique gate structure for reducing shorts between word lines on charge-trapping flash cell memory. In the early stage of developing sub-45 nm half-pitch word line by a self-aligned double patterning (SADP) technology, the cell array suffered from abnormal intrinsic word line-to-word line shorts, ca. 96.3% of the bridge rate on the 72 Mb cell memory, due to the formation of polysilicon residues called stringers. The increase of polysilicon over-etching to eliminate stringers involves a trade-off between the removal efficiency of stringers and the feature size maintenance. Hence, a novel bottle-shaped gate profile was tailor-made and studied. As a result, the bridge rates are dramatically suppressed to 0%~10% on the low-density flash cells and ca. 22% in average on the high-density 512 Mb flash cell memory. The novel bottle-shaped gate structure is successfully implemented in advanced charge-trapping flash memory development.
We have developed a new Self-aligned poly (SAP) process to improve the tunnel oxide integrity by optimizing the shallow trench isolation (STI) corner rounding profile and reducing the local oxide thinning effect. It i...
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We have developed a new Self-aligned poly (SAP) process to improve the tunnel oxide integrity by optimizing the shallow trench isolation (STI) corner rounding profile and reducing the local oxide thinning effect. It is found that double in-situ steam generation (ISSG) liner oxides can effectively improve the STI corner rounding. As for the local oxide thinning effect, the composite pad dielectrics (C-Pad) composed of SiO 2 /poly-Si are good to prevent local thinning of tunnel oxide at STI corner. Moreover, using ISSG tunnel oxide can further reduce the local oxide thinning effect. Excellent breakdown characteristics of tunnel oxide by optimizing the key technologies have been verified in this work.
Previous study has shown that off-axis illumination (OAI) which employs duplicate conventional source shape such as double dipóle, double annular or double quadrupole can reduce the effect of line width fluctuati...
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This paper identifies the defect adders, for example, post hard-mask etch residue, post metal etch residue, and blocked etch metal island and investigates the removal characteristics of these defects within the oxide-...
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This paper identifies the defect adders, for example, post hard-mask etch residue, post metal etch residue, and blocked etch metal island and investigates the removal characteristics of these defects within the oxide-masked Al etching process sequence. Post hard-mask etch residue containing C atom is related to the hardening of photoresist after the conventional post-RIE ashing at 275C. An in situ O2 -based plasma ashing on RIE etcher was developed to prevent the photoresist hardening from the high-ashing temperature;followed wet stripping could successfully eliminate such hardened polymeric residue. Post metal etch residue was caused from the attack of the Al sidewall by Cl atoms, and too much CHF3 addition in the Al main etch step passivated the surface of Al resulting in poor capability to remove the Al-containing residue. The lower addition of CHF3 in the Al main etch step would benefit from the residue removal. One possibility of blocked etch metal island creating was due to the micromasking formed on the opening of TiN during the hard-mask patterning. We report that an additional TiN surface pretreatment with the Ar/CHF3 /N2 plasmas could reduce the impact of the micromasking residues on blocked metal etch.
In accordance with continuing push for smaller and faster electronics, there is strong demand for further miniaturization and higher performance of mobile and other digital devices. Three-dimensional interconnect with...
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In accordance with continuing push for smaller and faster electronics, there is strong demand for further miniaturization and higher performance of mobile and other digital devices. Three-dimensional interconnect with through silicon via is the most potential solution to extend Moore's Law. In recent years, 3D interconnect(3DIC) technology is attracting the interest of university, research institutes, Fab engineers, package engineers, chip designers and equipment manufacturers turn to 3D research and development efforts. It has the potential to be the mainstream for chip manufacturing of in the near future. This technology had the benefits of cost, performance, form factor and heterogeneous integration for chips manufacturing. But thermal dissipation, process technology and infrastructure readiness still are the top three issues for success of 3DIC. Cost and manufacturability will be the key knob to enable this technology. In this paper, we demonstrated a production worthy 3DIC technology with IC Fab infrastructure. Key modules' process and electrical results are reported. Well-controlled high aspect ratio (AR=8:1 and AR=15:1) through silicon vias (TSVs) were successfully filled with both copper (Cu) and tungsten (W). Metal to metal diffusion bonding was demonstrated with good uniformity. For the first time, a cost effective wafer thinning without decreasing effective area by a proprietary process is described. Chains were formed between two wafers through bonded copper structures and electrically probed on the top wafer which had been thinned. Yielding 20 K through silicon vias with aspect ratio of 15:1 and resistance of through silicon via chain are demonstrated.
The process integration of novel Cu CMP's barrier slurry for the 45nm-node non-capped ultra low-k (ULK, k < 2.5) technology is reported. The slurry, based on a 'self-stop' concept, was designed to mitig...
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The process integration of novel Cu CMP's barrier slurry for the 45nm-node non-capped ultra low-k (ULK, k < 2.5) technology is reported. The slurry, based on a 'self-stop' concept, was designed to mitigate the impact of ULK damage, such as unexpectedly high removal rate and drifted polish selectivity, by etching-related processes. After analyzing the pattern density effect and the damaged layer, a film-damage-recovery process and CMP soft-landing approach were also integrated in order to have an enhanced Rs stability
Owing to the k extendability of porogen LK formed with the incorporation and removal of organic porogen precursors, the porogen LK is the competitive candidate for inter-metal dielectrics (IMDs) of 65nm generation and...
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ISBN:
(纸本)142440181X
Owing to the k extendability of porogen LK formed with the incorporation and removal of organic porogen precursors, the porogen LK is the competitive candidate for inter-metal dielectrics (IMDs) of 65nm generation and beyond. However, its porosity raises major challenges in the Cu/LK integration. Chemical and metal penetrability of the porogen LK film revealed the necessity of a protective pore sealing layer in dual damascene. Pore sealing materials were evaluated and SiC x H y film demonstrated exceptional barrier property against metal diffusion and good step coverage over the trench profile. By introduction of this SiC x H y layer, 10% capacitance reduction was achieved despite the higher k of the material. With the well-controlled thickness, SiC x H y pore sealing also demonstrated no via-Rc shift compared to the scheme without pore sealing, therefore excellent protection on the trench structure without via performance degradation was accomplished
The die edge-seals and circuit under fad (CUF) are structurally optimized through 3D finite element analysis (FEA). Die edge-seals having the mechanically reinforced structure units are demonstrated essential. It is a...
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The die edge-seals and circuit under fad (CUF) are structurally optimized through 3D finite element analysis (FEA). Die edge-seals having the mechanically reinforced structure units are demonstrated essential. It is also shown that FEA help extract useful structural design concepts for CUP. The Poisson effects leading to a dual-ring-shaped high stress distribution area are confirmed to be detrimental for wire bonding and wire-pull tests. Excellent agreements are obtained as compared with the experimental data
The concerns of barrier integrity in applications of porous low-k (PLK) dielectrics for Cu dual damascene (DD) interconnects have been dismissed with a novel self-assembled monolayer (SAM) approach. Results showed a 7...
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The concerns of barrier integrity in applications of porous low-k (PLK) dielectrics for Cu dual damascene (DD) interconnects have been dismissed with a novel self-assembled monolayer (SAM) approach. Results showed a 7% improvement in the PLK/TaN-interface adhesion with SAM. SAM also achieved a 30% improvement in line-line (L-L) breakdown tolerance and 100X lower leakage current @ lMV/cm when applied to Cu/PLK interconnect with k=2.5 and pore size ~ 2.0 nm without compromising effective K, K eff
In accordance with continuing push for smaller and faster electronics, there is strong demand for further miniaturization and higher performance of mobile and other digital devices. Three-dimensional interconnect with...
详细信息
In accordance with continuing push for smaller and faster electronics, there is strong demand for further miniaturization and higher performance of mobile and other digital devices. Three-dimensional interconnect with through silicon via is one of the solution with best potential to extend Moore's Law. 3D interconnect had the benefits of lower cost, higher performance, smaller form factor and heterogeneous integration for chips manufacturing. Thermal dissipation, process technology and circuit design are the top three issues for 3D IC success. For Si processing, the major challenges are the patterning and the fill of the through wafer via, wafer thinning, die/wafer bonding and its alignment. We need to carefully address those issues before we can proceed to mass production
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