For the first time, trap density at SiO2/Si interface, HfO2/SiO2 interface, and HfO2 bulk of stacked HfO2/SiO2 dielectrics are quantified respectively with a simple charge pumping method. It was found that the amount ...
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ISBN:
(纸本)078038315X
For the first time, trap density at SiO2/Si interface, HfO2/SiO2 interface, and HfO2 bulk of stacked HfO2/SiO2 dielectrics are quantified respectively with a simple charge pumping method. It was found that the amount of each individual type of traps can be well correlated to specific process conditions as well as device performance, which makes such innovative characterization method very powerful for process optimization of high-k dielectrics.
A novel UV photo-oxidation (UVPO) is developed for ideal "atomic-layer oxidation" with excellent thickness control down to 4Å, which is very promising for interfacial layer formation of scaled gate oxyn...
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A novel UV photo-oxidation (UVPO) is developed for ideal "atomic-layer oxidation" with excellent thickness control down to 4Å, which is very promising for interfacial layer formation of scaled gate oxynitride and high-k applications. In addition, ultrathin oxynitride (EOT<12Å) using a newly-developed low ion-energy nitrogen plasma (30% plasma damage reduction) in combination with thermal nitridation is demonstrated for n/pMOSFET performance optimization. Finally, device performance is further enhanced (+7% of nFET Ion-Ioff by tensile stress with negligible impact on pFET) by mechanical stress modulation from strain contact-etch-stop layer (CESL). The proposed technologies represent an efficient approach to realize ultrathin gate oxynitride toward sub-65nm CMOS production.
A hybrid dual damascene interconnect approach with organic ultra-low-k for gap filling has been demonstrated. Traditional PR approach with via-first process for dual damascene suffers from ashing damage for CVD ultra-...
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For the first time, trap density at SiO/sub 2//Si interface, HfO/sub 2//SiO/sub 2/ interface, and HfO/sub 2/ bulk of stacked HfO/sub 2//SiO/sub 2/ dielectrics are quantified respectively with a simple charge pumping m...
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For the first time, trap density at SiO/sub 2//Si interface, HfO/sub 2//SiO/sub 2/ interface, and HfO/sub 2/ bulk of stacked HfO/sub 2//SiO/sub 2/ dielectrics are quantified respectively with a simple charge pumping method. It was found that the amount of each individual type of traps can be well correlated to specific process conditions as well as device performance, which makes such innovative characterization method very powerful for process optimization of high-k dielectrics.
Reliability concerns over the applications of porous low-k dielectrics for Cu dual damascene (DD) interconnects have been dismissed with novel film formation methods, patterning approaches and structure designs. Resul...
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ISBN:
(纸本)0780382897
Reliability concerns over the applications of porous low-k dielectrics for Cu dual damascene (DD) interconnects have been dismissed with novel film formation methods, patterning approaches and structure designs. Results showed that the BEOL time dependent dielectric breakdown (BEOL TDDB) performance of interconnects built using porous CVD LK's with k=2.2 and pore size /spl sim/2.8nm were not comprised with film pore integrity retained to have TDDB T/sub 63/ predicted to be 1 /spl times/ 10/sup 9/ yrs at 0.3 MV/cm and 125/spl deg/C. Further investigations also revealed that the impacts of weak mechanical and poor thermal properties associated with the LK material on its interconnect electromigration and stress migration performances can be demolished through various interface engineering with EM lifetimes of 0.12 /spl mu/m Cu lines or 0.13 /spl mu/m vias at 1 MA/cm/sup 2/ and 110/spl deg/C longer than 400k hrs or 150k hrs, and SM failure rate = 0 (>100% Re shift) for vias on all test structures after thermal annealing at 150/spl deg/C for 500 hrs.
A hybrid dual damascene interconnect approach with organic ultra-low-k for gap filling has been demonstrated. The traditional PR approach with via-first process for dual damascene suffers from ashing damage for CVD ul...
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A hybrid dual damascene interconnect approach with organic ultra-low-k for gap filling has been demonstrated. The traditional PR approach with via-first process for dual damascene suffers from ashing damage for CVD ultra-low-k. Our approach is able to circumvent the issues mentioned above without introducing process complication. Good sheet resistance control is obtained for trench etch without a middle stop layer. And good via resistance yield with good thermal stability is obtained as well. 21% of RC product reduction is obtained when it is compared with the PR approach for CVD ultra-low-k.
advanced BEOL materials matching in chemical, thermal, and mechanical properties remain a challenge to the industry. New failure modes associated with BEOL reliability hinder the mass production of Cu/low-k technology...
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ISBN:
(纸本)0780386841
advanced BEOL materials matching in chemical, thermal, and mechanical properties remain a challenge to the industry. New failure modes associated with BEOL reliability hinder the mass production of Cu/low-k technology. With 15% IMD effective-K reduction target, low-K, ESL, and metal pitch/height ratio optimization are crucial. Integrated module built-in reliability robustness is to assure stable production. Physical, electrical, reliability, and manufacturability aspects of individual module require full characterization. Implementations of proper queue-time control and iAPC between modules will minimize excursions and increase process window.
A novel UV photo-oxidation (UVPO) is developed for ideal "atomic-layer oxidation" with excellent thickness control down to 4/spl Aring/, which is very promising for interfacial layer formation of scaled gate...
详细信息
ISBN:
(纸本)0780382897
A novel UV photo-oxidation (UVPO) is developed for ideal "atomic-layer oxidation" with excellent thickness control down to 4/spl Aring/, which is very promising for interfacial layer formation of scaled gate oxynitride and high-k applications. In addition, ultrathin oxynitride (EOT<12/spl Aring/) using a newly-developed low ion-energy nitrogen plasma (30% plasma damage reduction) in combination with thermal nitridation is demonstrated for n/pMOSFET performance optimization. Finally, device performance is further enhanced (+7% of nFET Ion-Ioff by tensile stress with negligible impact on pFET) by mechanical stress modulation from strain contact-etch-stop layer (CESL). The proposed technologies represent an efficient approach to realize ultrathin gate oxynitride toward sub-65nm CMOS production.
Cu/porous low-k (PLK) with k/spl les/2.5 is the current choice to 65nm and beyond BEOL interconnect technologies. However, critical concerns of the weak physical and chemical structures of PLK (k/spl les/2.5) films on...
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Cu/porous low-k (PLK) with k/spl les/2.5 is the current choice to 65nm and beyond BEOL interconnect technologies. However, critical concerns of the weak physical and chemical structures of PLK (k/spl les/2.5) films on their integration compatibilities, such as CMP defectivity and trench bottom/via smoothness, electrical performances, such as etching/ashing film damaging, and reliability performances, such as electromigration (EM), stress migration (SM) and time-dependent dielectric breakdown (TDDB), still challenge their application feasibility. A novel in-situ formed trench-porous (k=2.5) and via-dense (k=2.7) k=2.5/2.7 bilayer film design was proposed in this study to overcome these facing issues. Cu/PLK DD study results showed that CMP defectivity was /spl sim/4/spl times/ improved and trench bottom was smoothened with a k=2.5/2,7 bilayer PLK approach. Electrical performances using this approach also showed that film damaging from DD etching/ashing was reduced with the higher chemical resistance of the via in the bilayer. Reliability study results demonstrated that an /spl sim/ 2000/spl times/ better DD TDDB lifetime was achieved due to smooth trench bottoms. When changing from Cu/k=2.5 single layer to Cu/k=2.5/2.7 bilayer, SM and EM performances were not impacted. Moreover, with >405 improved hardness and film adhesion the bilayer PLK approach highlights a potential direction to improve Cu/k=2.5 PLK manufacturability in packaging. All these results indicate that this Cu/bilayer BEOL interconnection applicable for 65 nm and beyond generation CMOS technologies.
An overview of the process performance of Stress Free Polishing technology (SFP) for copper removal at sub 90 nm nodes is presented in this paper. A brief description of the SFP process and polishing characteristics i...
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