Nine-metal-level (9ML) Cu/CVD low-k dielectric with k=2.2, Cu/LK (k=2.2), damascene integration on 300mm wafers for 90/65nm generation has been successfully demonstrated for the first time. To minimize line-line capac...
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Nine-metal-level (9ML) Cu/CVD low-k dielectric with k=2.2, Cu/LK (k=2.2), damascene integration on 300mm wafers for 90/65nm generation has been successfully demonstrated for the first time. To minimize line-line capacitance for least BEOL interconnect RC delay, no higherk cap for Cu CMP or higher-k middle etch stop layers for metal trench etching were used in inter metal dielectric (IMD) film stacking. Integration challenges in the Cu/LK (k=2.2) damascene building were overcome by novel approaches in IMD film processing, Cu CMP and patterning. Excellent physical, electrical, reliability, and packaging results from this Cu/LK (k=2.2) BEOL interconnects are demonstrated.
An overview of the process performance of Stress Free Polishing technology (SFP) for copper removal at sub 90 nm nodes is presented in this paper. A brief description of the SFP process and polishing characteristics i...
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An overview of the process performance of Stress Free Polishing technology (SFP) for copper removal at sub 90 nm nodes is presented in this paper. A brief description of the SFP process and polishing characteristics is provided along with electrical results. Dependence of post SFP copper surface quality on the roughness of the incoming films and post plating anneal conditions is also discussed.
In this article, we present a novel via-sealing-architecture (VISA) dual damascene patterning technology, featuring with immunity from PR poisoning and ash-induced degradation of porous low-k dielectrics, and planar s...
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A novel remote plasma-enhanced atomic layer deposition (RPEALD) silicon nitride technology is developed in a production-worthy tool for nitride/oxide (N/O) stack gate dielectric. Ultrathin N/O stack (EOT-13Å) is ...
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A novel PECVD porous low-k material with k=2.5, LK(k=2.5), has been successfully integrated with Cu for 90 nm generation BEOL interconnect technology on 300 mm wafers. Fundamental film studies showed that this low-k m...
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A novel PECVD porous low-k material with k=2.5, LK(k=2.5), has been successfully integrated with Cu for 90 nm generation BEOL interconnect technology on 300 mm wafers. Fundamental film studies showed that this low-k material is thermally stable up to 400/spl deg/C and can be strongly adhered to various dielectric films. Electrical measurement results from the Cu/LK(k=2.5) damascene interconnect showed tight and 100%-yielded distributions in 0.12/0.12 /spl mu/m interline leakage, one million 0.13 /spl mu/m viachain via Rc and 0.12 /spl mu/m Cu line Rs. To maximize the Cu/LK(k=2.5) interconnect capacitance performance, no middle etch stop layer and no top CMP cap were used in the dielectric film stacking. The final k value of the LK(k=2.5) after integration was retained at 2.5 using an optimized PR ashing chemistry by comparing the Cu/LK(2.5) 0.12/0.12 /spl mu/m interline capacitance to a Cu/LK(3.0) one. The intrinsic BEOL time dependent dielectric breakdown (TDDB) lifetime, T/sub 63,/ of the Cu/LK(k=2.5) is predicted to be 4.56/spl times/10/sup 8/ yrs at 0.3 MV/cm and 125/spl deg/C. Further reliability evaluations of the Cu/LK(k=2.5) in electromigration (EM) and stress migration (SM) showed that its predicted T/sub 0.1/ EM lifetimes for 0.12 /spl mu/m Cu line or 0.13 /spl mu/m via at 1 MA/cm2 and 110/spl deg/C are 152k hrs or 144k hrs, and its SM failure rate (>10% shift in Rc) is zero after 500hr annealing at 175/spl deg/C. Finally, the packaging feasibility of this Cu/LK(k=2.5) damascene interconnect was also demonstrated using current wire bonding technologies.
This paper describes a 90 nm System-on-a-chip (SoC) technology with modular quadruple gate oxides (16, 28, 50, 64 /spl Aring/) on the same chip allowing integration of optimized transistors operating at supply voltage...
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This paper describes a 90 nm System-on-a-chip (SoC) technology with modular quadruple gate oxides (16, 28, 50, 64 /spl Aring/) on the same chip allowing integration of optimized transistors operating at supply voltages of 1, 1.2, 1.8, 2.5 and 3.3 Volts for different circuit applications. The proposed modular gate oxide process with pre-gate nitrogen implant was shown to be superior to conventional grow-etch-grow approach in terms of gate leakage current, integrity and interface quality of the multiple gate oxides. A high current drive of 1020/390 /spl mu/A//spl mu/m was demonstrated for N/P channel core transistors.
In this article, we present a novel via-sealing-architecture (VISA) dual damascene patterning technology, featuring with immunity from PR poisoning and ash-induced degradation of porous low-k dielectrics, and planar s...
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In this article, we present a novel via-sealing-architecture (VISA) dual damascene patterning technology, featuring with immunity from PR poisoning and ash-induced degradation of porous low-k dielectrics, and planar surface topology for both via and trench lithography. Its electrical performance is demonstrated by integrating Cu and porous organosilicate glass (OSG), /spl kappa/=2.2, with 90 nm design rule and 193 nm lithography on the 300 mm wafer. The new architecture, which consists of depositing hard-mask dielectrics over the etched hole to form a sealed structure, enables this patterning technology extending to 65 nm generation and below without influenced by low-k materials and lithography technology.
A novel remote plasma-enhanced atomic layer deposition (RPEALD) silicon nitride technology is developed in a production-worthy tool for nitride/oxide (N/O) stack gate dielectric. Ultrathin N/O stack (EOT/spl sim/13 /s...
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ISBN:
(纸本)489114033X
A novel remote plasma-enhanced atomic layer deposition (RPEALD) silicon nitride technology is developed in a production-worthy tool for nitride/oxide (N/O) stack gate dielectric. Ultrathin N/O stack (EOT/spl sim/13 /spl Aring/) is realized with 50X gate leakage current reduction over thermal oxides. In addition to drastic gate current reduction, devices with RPEALD N/O stack and plasma-nitrided base oxide also exhibit well-behaved device performance and superior reliability characteristics (Qbd, TDDB, NBTI), very promising for sub-65 nm low power CMOS applications.
Surface voltage (Vsurf) measurements using a non-contact mode measurement (NCMM) tool on bare thick oxide wafers have been widely used for the characterization of plasma charging damage in BEOL processes. In this pape...
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Surface voltage (Vsurf) measurements using a non-contact mode measurement (NCMM) tool on bare thick oxide wafers have been widely used for the characterization of plasma charging damage in BEOL processes. In this paper, plasma damage to gate oxide in a plasma nitridation (PN) system has been systematically studied by an NCMM system on bare oxide wafers. The results demonstrate that conventional V/sub surf/ measurement on thick oxide bare wafers has the sensitivity to detect the positive charge induced by the PN process and to characterize the plasma uniformity, but this method might underestimate the damage to gate oxide. It is found that both D/sub it/ and Q/sub tot/ measurements on very thin oxide are more accurate methods to quantify the plasma damage. However, only D/sub it/ correlates well with device performance. The findings of this study provide a time saving and cost effective method for PN process optimization and process monitoring.
As the device dimension continues to shrink, the need for a thinner barrier for copper has risen in order to meet the requirements for future device performance. The conventional barrier process by physical vapor depo...
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As the device dimension continues to shrink, the need for a thinner barrier for copper has risen in order to meet the requirements for future device performance. The conventional barrier process by physical vapor deposition (PVD) has the limitation to achieve conformal step coverage across the dual damascene structure , and therefore would face a bottleneck when the thickness reduction is required. In this work, the atomic layer deposition (ALD) technique is applied for the TaN barrier process of a 90 nm generation copper dual damascene integration with low-k dielectrics of k=3.0. The ALD technique could not only provide a conformal step coverage on both trenches and vias, it could also allows reasonable thickness control for thickness of the order of 10 /spl Aring/. The integration results show that ALD TaN has promising electrical performance on sheet resistance, via resistance, and line-to-line leakage, and it also has superior reliability performance on electromigration, stress migration, and bias temperature test as compared with conventional PVD TaN.
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