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检索条件"机构=Advanced Module Technology Development"
88 条 记 录,以下是71-80 订阅
advanced 300mm Cu/CVD LK (k=2.2) Multilevel Damascene Integration for 90/65nm Generation BEOL Interconnect Technologies
Advanced 300mm Cu/CVD LK (k=2.2) Multilevel Damascene Integr...
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2003 Symposium on VLSI technology
作者: Li, L.P. Lu, Y.C. Lu, H.H. Yang, Y.L. Lin, C.H. Lin, K.C. Chen, B.T. Liang, M. Jang, S.M. Liang, M.S. Advanced Module Technology Division Research and Development Taiwan Semiconduct. Mfg. Company Science-Based Industrial Park Hsin-Chu Taiwan
Nine-metal-level (9ML) Cu/CVD low-k dielectric with k=2.2, Cu/LK (k=2.2), damascene integration on 300mm wafers for 90/65nm generation has been successfully demonstrated for the first time. To minimize line-line capac... 详细信息
来源: 评论
An overview of stress free polishing of Cu with ultra low-k(k<2.0) films
An overview of stress free polishing of Cu with ultra low-k(...
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IEEE International Conference on Interconnect technology
作者: J. Pallinti S. Lakshminarayanan W. Barth P. Wright M. Lu S. Reder L. Kwak W. Catabay D. Wang F. Ho Advanced Process Module Development LSI Logic Corporation Gresham OR USA Advanced Technology Development LSI Logic Corporation Milpitas CA USA
An overview of the process performance of Stress Free Polishing technology (SFP) for copper removal at sub 90 nm nodes is presented in this paper. A brief description of the SFP process and polishing characteristics i... 详细信息
来源: 评论
Novel dual damascene patterning technology for ultra low-κ dielectrics
Novel dual damascene patterning technology for ultra low-κ ...
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2003 IEEE International Interconnect technology Conference, IITC 2003
作者: Yeh, C.N. Lu, Y.C. Wu, T.C. Lu, H.H. Chen, C.C. Tao, H.J. Liang, M.S. Advanced Module Technology Division Research and Development TSMC Science-Based Industrial Park Hsin-Chu300-77 Taiwan Micropatterning Technology Division Research and Development TSMC Science-Based Industrial Park No. 6 Li-Hsin Rd. 6 Hsin-Chu300-77 Taiwan
In this article, we present a novel via-sealing-architecture (VISA) dual damascene patterning technology, featuring with immunity from PR poisoning and ash-induced degradation of porous low-k dielectrics, and planar s... 详细信息
来源: 评论
Remote Plasma-Enhanced Atomic Layer Deposition (RPEAJLD) Nitride/Oxide Gate Dielectric for Sub-65nm Low Standby Power CMOS Application
Remote Plasma-Enhanced Atomic Layer Deposition (RPEAJLD) Nit...
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2003 Symposium on VLSI technology
作者: Chen, Chi-Chun Lee, T.-L. Lee, D.-Y. Chang, V.S. Lin, H.-C. Chen, S.-C. Huang, T.-Y. Liang, M.-S. Advanced Module Technology Division Research & Development Taiwan Semiconductor Manufacturing Co. Ltd. Taiwan Institute of Electronics National Chiao Tung University Taiwan National Nano Device Laboratory Taiwan
A novel remote plasma-enhanced atomic layer deposition (RPEALD) silicon nitride technology is developed in a production-worthy tool for nitride/oxide (N/O) stack gate dielectric. Ultrathin N/O stack (EOT-13Å) is ... 详细信息
来源: 评论
Fundamental, integration, and reliability of the 90 nm generation Cu/LK(k=2.5) damascene using a novel PECVD porous low-k dielectric film
Fundamental, integration, and reliability of the 90 nm gener...
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IEEE International Conference on Interconnect technology
作者: Y.L. Yang L.P. Li H. Ouyang Y.C. Lu H.H. Lu C.H. Lin K.C. Lin S.M. Jang M.S. Liang Department of Dielectrics and CMP Advanced Module Technology Division Research & Development Taiwan Semiconductor Manufacturing Company Limited Hsinchu Taiwan
A novel PECVD porous low-k material with k=2.5, LK(k=2.5), has been successfully integrated with Cu for 90 nm generation BEOL interconnect technology on 300 mm wafers. Fundamental film studies showed that this low-k m... 详细信息
来源: 评论
A 90 nm CMOS technology with modular quadruple gate oxides for advanced SoC applications
A 90 nm CMOS technology with modular quadruple gate oxides f...
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Annual International Symposium on Reliability Physics
作者: M.R. Mirabedini V.P. Gopinath A. Kamath M.Y. Lee W.J. Hsia V. Hornback Y. Le A. Badowski B. Baylis E. Li S. Prasad O. Kobozeva J. Haywood W. Catabay W.C. Yeh Advanced Technology Development LSI Logic Corporation Milpitas CA USA Process Module Development LSI Logic Corporation Gresham OR USA LSI Logic Corporation Santa Clara CA USA
This paper describes a 90 nm System-on-a-chip (SoC) technology with modular quadruple gate oxides (16, 28, 50, 64 /spl Aring/) on the same chip allowing integration of optimized transistors operating at supply voltage... 详细信息
来源: 评论
Novel dual damascene patterning technology for ultra low-/spl kappa/ dielectrics
Novel dual damascene patterning technology for ultra low-/sp...
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IEEE International Conference on Interconnect technology
作者: C.N. Yeh Y.C. Lu T.C. Wu H.H. Lu C.C. Chen H.J. Tao M.S. Liang Advanced Module Technology Division Research and Development Taiwan Semiconductor Manufacturing Company Limited Hsinchu Taiwan Micropatterning Technology Division Research and Development Taiwan Semiconductor Manufacturing Company Limited Hsinchu Taiwan Division Research and Development Taiwan Semiconductor Manufacturing Company Limited Hsinchu Taiwan
In this article, we present a novel via-sealing-architecture (VISA) dual damascene patterning technology, featuring with immunity from PR poisoning and ash-induced degradation of porous low-k dielectrics, and planar s... 详细信息
来源: 评论
Remote plasma-enhanced atomic layer deposition (RPEALD) nitride/oxide gate dielectric for sub-65 nm low standby power CMOS application
Remote plasma-enhanced atomic layer deposition (RPEALD) nitr...
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Symposium on VLSI technology
作者: Chi-Chun Chen T.-L. Lee D.-Y. Lee V.S. Chang H.-C. Lin S.-C. Chen T.-Y. Huang M.-S. Liang Advanced Modulf Technology Division Research & Development Taiwan Semiconducfor Manufacturing Company Limited Taiwan Advanced Module Technology Division Taiwan Semiconductor Manufacturing Co. Ltd. Adv. Module Technol. Div. Taiwan Semicond. Manuf. Co. Hsin-Chu Taiwan Advanced Modulf Technology Division Research & Development Taiwan Semiconductor Manufacturing Company Limited Institute of Electronics National Chiao Tung University Institute of Electronics National Chiao Tung University Taiwan
A novel remote plasma-enhanced atomic layer deposition (RPEALD) silicon nitride technology is developed in a production-worthy tool for nitride/oxide (N/O) stack gate dielectric. Ultrathin N/O stack (EOT/spl sim/13 /s... 详细信息
来源: 评论
Direct measurement of gate oxide damage from plasma nitridation process
Direct measurement of gate oxide damage from plasma nitridat...
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International Symposium on Plasma- and Process-Induced Damage
作者: Y. Jin C.-C. Chen V.S. Chang D.-Y. Leel T.-L. Lee S.-C. Chen M.-S. Liang Institute of Electronics National Chiao Tung University Hsinchu Taiwan Advanced Module Technology Division Research & Development Taiwan Semiconductor Manufacture Co. Ltd. Hsin Chu Taiwan R.O.C. Advanced Module Technologv Division Research & Development Taiwan Semiconductor Manufacturing Company Limited Hsinchu Taiwan Institute of Electronics National Chiao Tung University Hsin-Chu Taiwan R.O.C.
Surface voltage (Vsurf) measurements using a non-contact mode measurement (NCMM) tool on bare thick oxide wafers have been widely used for the characterization of plasma charging damage in BEOL processes. In this pape... 详细信息
来源: 评论
A 90 nm generation copper dual damascene technology with ALD TaN barrier
A 90 nm generation copper dual damascene technology with ALD...
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International Electron Devices Meeting (IEDM)
作者: C.H. Peng C.H. Hsieh C.L. Huang J.C. Lin M.H. Tsai M.W. Lin C.L. Chang W.S. Shue M.S. Liang Advanced Module Technology Development Division Research and Development Taiwan Semiconductor Manufacturing Company Limited Hsinchu Taiwan
As the device dimension continues to shrink, the need for a thinner barrier for copper has risen in order to meet the requirements for future device performance. The conventional barrier process by physical vapor depo... 详细信息
来源: 评论