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Symposium on VLSI technology

作者： S.M. Jang Y.H. Chen T.J. Chou S.N. Lee C.C. Chen T.C. Tseng B.T. Chen S.Y. Chang C.H. Yu M.S. Liang Advanced Module Technology Division Research and Development Taiwan Semiconductor Manufacturing Company Hsinchu Taiwan

A spin-on dielectric (SOD, k=2.2) has been integrated with Cu for 0.10/0.07 /spl mu/m generations. To minimize interconnect capacitance, conventional CVD cap layer (k=4.5-7.5) is replaced by a SOD dielectric (k=2.9) and no stop layer for trench etch is used for the porous inter-metal dielectric (IMD). The issue of photoresist poisoning is resolved by nitrogen-free IMD processing. Using polymeric abrasive together with polishing parameters designed in a low friction domain for planarization, 6-level Cu/porous SOD multilevel interconnect is demonstrated for the first time. Electrical testing shows promising results for the high-performance dual damascene structure.

关键词： Thermal stresses Etching Resists Tensile stress Silicon carbide Capacitance Testing Curing Dielectric materials Silicon compounds

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Design rule methodology to improve the manufacturability of the copper CMP process

Design rule methodology to improve the manufacturability of ...

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IEEE International Conference on Interconnect technology

作者： S. Lakshminarayanan P. Wright J. Pallinti Process Technology development LSI Logic Corporation Santa Clara CA USA Process Module development and advanced research Gresham OR USA

A systematic approach to generate design rules and layout guidelines for damascene metal layers that enhance the robustness and manufacturability of designs is presented. The intra-die sheet resistance variation due to line width and pattern density effects is characterized for single and multi-level interconnects and the feature interaction distance is determined to be about 30 /spl mu/m. It is shown that the best way to minimize the sheet resistance spread is by implementing rules for the minimum and maximum space between any two features as a function of their widths.

关键词： Design methodology Manufacturing processes Copper Integrated circuit interconnections Robustness Clocks Testing Surfaces Large scale integration Logic design

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advanced metal barrier free Cu damascene interconnects with PECVD silicon carbide barriers for 90/65-nm BEOL technology

Advanced metal barrier free Cu damascene interconnects with ...

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International Electron Devices Meeting (IEDM)

作者： Z.C. Wu Y.C. Lu C.C. Chiang M.C. Chen B.T. Chen G.J. Wang Y.T. Chen J.L. Huang S.M. Jang M.S. Liang Department of Dielectric and Cmp Advanced Module Technology Division Research and Development Taiwan Semiconductor Manufacturing Company Hsinchu Taiwan Department of Electronics Engineering National Chiao Tung University Hsinchu Taiwan Department of Dielectric and CMF Advanced Module Technology Division Research and Development Taiwan Semiconductor Manufacturing Company Hsinchu Taiwan Department of Dielectric and CMP Advanced Module Technology Division Research and Development Taiwan Semiconductor Manufacturing Company Hsinchu Taiwan

advanced metal barrier free (MBF) Cu dual damascene interconnects (DDIs) have been successfully fabricated using a low-k CVD OSG (k=2.5) and PECVD silicon carbides for the first time. With PECVD silicon carbides replacing TaN, the Cu DDIs thus built showed 8% better in interconnect RC delay, 36% lower in via resistance and three orders of magnitude lower in line-line leakage at 200/spl deg/C. The newly developed technology also enhanced Cu TDDB lifetime by more than three orders of magnitude. On the MBF DDIs, 15%-faster 90-nm CMOS device operation has been achieved, which makes the newly developed MBF Cu DDI technology promising for high performance sub-90 nm CMOS devices and beyond.

关键词： Silicon carbide Delay CMOS technology Atherosclerosis Research and development Semiconductor device manufacture Temperature Acceleration Dielectric breakdown Threshold voltage

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Thermo-mechanical reliability of the benzocyclobuten (BCB) film in a WLCSP process

Thermo-mechanical reliability of the benzocyclobuten (BCB) f...

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International Symposium on Electronic Materials and Packaging

作者： K.O. Lee Jin Yu J.Y. Kim I.S. Park Department of Materials Science & Engineering Korea Advanced Institute of Science and Technology Center for Electronic Packaging Materials Daejeon South Korea Advanced package development team Package & Module R & D Center Hynix Semiconductor Inc. South Korea

ISBN: (纸本)0780371577

A new WLCSP process which enables reliable fabrication of high-performance and low cost package has been developed based on the low dielectric passivation layer. The fabrication process can be reduced by using the newly developed photosensitive-BCB and a conventional photolithography process. However, cracks frequently nucleating on the BCB poses serious reliability issues. In order to prevent the crack generation, the stresses in the BCB layer were reduced by optimizing the relative thickness of the BCB and the underlying stress buffer layer(SBL), and by stabilizing the BCB microstructure with optimal photolithography processes. The microstructure of the BCB was investigated by measuring the molecular weight, the cross link element intensity and the glass transition temperature.

关键词： Thermomechanical processes Fabrication Lithography Stress Microstructure Costs Packaging Dielectrics Passivation Weight measurement

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Defect reduction of copper BEOL for advanced ULSI interconnect

Defect reduction of copper BEOL for advanced ULSI interconne...

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IEEE International Conference on Interconnect technology

作者： Hsueh-Chung Chen Teng-Chun Tsai Yi-Min Huang Chao-Hui Huang Chien-Hung Chen Yung-Tsung Wei Ming-Sheng Yang Juan-Yuan Wu Tri-Rung Yew Jen-Kon Chen United Foundry Service United Microelectronics Corporation Limited Hopewell Junction NY USA Advanced Technology Development Department United Microelectronics Corporation Limited Hsinchu Taiwan Division Process Module A Department United Microelectronics Corporation Limited Hsinchu Taiwan

ISBN: (纸本)0780366786

In this paper, a full discussion of the defect reduction in copper BEOL technology of a 1P/3M logic product is presented for the first time. Defectivity is inspected from AEI to CMP on various metal levels. Defectivity is classified into non CMP-related type and CMP-related type. Most of the non-CMP type defects are foreign matter coming from the environment or from the processing residues. They can be effectively removed in a CMP step, as long as they were not trapped in the metal trench. On the other hand, the CMP-related type defects impact the consecutive process and yield significantly. Examples of the killer defects are slurry residues, corrosion, and scratching. Prevention and reduction of defects is discussed. Product yield is greatly improved after the reduction of defectivity.

关键词： Copper Ultra large scale integration Corrosion Slurries Microelectronics Dielectric materials Atherosclerosis Chemical vapor deposition Chemical processes Inspection

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Affordability, logistics R&D and fleet systems

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NAVAL ENGINEERS JOURNAL 1996年第3期108卷 199-213页

作者： Schulte, DP Skolnick, A He has supported the development and operation of several naval systems including advanced component selection for Trident II fire control and navigation systems. He served as branch manager of the Surface Ship ASW Combat System Branch which acted as the acquisition engineering agent for the AN/SQQ-89 Surface Ship Anti-Submarine Warfare Weapon System. He was then selected to manage the Module Engineering Department which provided engineering support to numerous naval systems including the AN/BSY-1 Submarine Combat System and the Trident II fire control and navigation system. He then served as the deputy program manager for NAVSEA Progressive Maintenance (2M/ATE). He holds a B.S. degree in Electrical Engineering from Purdue University and currently is pursuing a Maste's degree in Public Environmental Affairs at Indiana University—Purdue University Indianapolis. He served at Applied Physics Laboratory/The Johns Hopkins University in missile development then aboard USS Boston (CAG-1) and played leading roles in several weapon system developments (Regulus Terrier Tartar Talos) inertial navigation (Polaris) deep submergence (DSRV) and advanced ship designs (SES). He later was director Combat System Integration Naval Sea Systems Command and head Combat Projects Naval Ship Engineering Center. He led the Navy's High Energy Lasers and Directed Energy Weapons development efforts. He was vice president advanced technology at Operations Research Inc. and vice president maritime engineering at Defense Group Inc. before starting SSC in 1991. Dr. Skolnick holds a B.S. degree in Mathematics and Economics Queens College an M.A. degree in Mathematics and Philosophy Columbia University an M.S. degree in Electrical/Aeronautical Engineering U.S. Naval Postgraduate School and a Ph.D. in Electrical Engineering and Applied Mathematics from Polytechnic University in New York. He is the author of many published papers on engineering design issues source selection procedures and large-scale complex technology problems

The Fleet continues to require high performance systems that can operate with dependability in the seas' unforgiving environments and under hostile action. Those demands are not new. What has changed is the urgent priority formerly assigned to national defense issues. The arguments for continued superpower military strength are now roiled in politics along with unsettled budgets and uncertain force level projections. Current expectations revolve about indefinite fiscal and operational issues (difficult funding constraints and broadband threats). In the actual event of ''doing more with less,'' a practical response is to apply the creative power available from sound engineering judgement and the crucible of experience to the immediate needs of the Fleet. The attempt to shorten the path between advanced development effort and Fleet use has been tried occasionally in the past, often, without exemplary results. The Sustainable Hardware and Affordable Readiness Practices (SHARP) program, is a generic R&D effort under OpNav sponsorship that has been working steadily on sensible solutions to product engineering problems. Armed today with fast-time, large-scale computation abilities and modern tools for technical problem solving coupled with specialized engineering knowledge, it has been refreshed and is underway satisfying existing Fleet needs. The relationship between fully responsive engineering services and current operational needs is always demanding. The connection between advanced engineering development (6.3 category funds) and immediate Fleet usage brings added complexity and challenge, both technical and organizational. Illustrative examples of affordable engineering solutions to ''retain, revise, replace or retire'' questions are presented within the context of both Fleet realities and budgetary limitations. The discussion covers legacy system support, civil/military considerations and Fleet maintenance issues. It describes the substantial and critical payoffs i

关键词： Warships

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PARALLEL AND DISTRIBUTED TLM COMPUTATION WITH SIGNAL-PROCESSING FOR ELECTROMAGNETIC-FIELD MODELING

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INTERNATIONAL JOURNAL OF NUMERICAL MODELLING-ELECTRONIC NETWORKS DEVICES AND FIELDS 1995年第3-4期8卷 169-185页

作者： SO, PPM ESWARAPPA, C HOEFER, WJR NSERC/MPR Teltech Research Chair in RF Engineering Department of Electrical and Computer Engineering University of Victoria Victoria British Columbia V8W 3P6 Canada Poman So received his B.Sc. degree in computer science and physics from the University of Toronto Toronto Onatario Canada in 1985. He obtained his B.A. Sc. and M.A.Sc. degrees in electrical engineering (summa cum laude) from the University of Ottawa Ottawa Ontario Canada in 1987 and 1989 respectively. Mr So was a research engineer in the University of Ottawa from January 1989 to October 1991 his research interests included CAD techniques of microwave circuits and numerical methods for electromagnetic wave modelling. He specialized in the development of electromagnetic engineering CAD software and successfully implemented a number of electromagnetic wave simulators based on the two-dimensional and three-dimensional transmission-line matrix methods. From August 1990 to February 1991 he accompanied Professor W. J. R. Hoefer to Rome Italy and Sophia Antiopolas France. During that time he implemented a parallel version of the 3D-TLM simulator for the CM-2 Connection Machine using C-Star and X Windows Library. He is a research engineer and a Ph.D. student at the University of Victoria Victoria British Columbia Canada. He ported the 2D- and 3D-TLM simulators to DECmpp 1200 massively parallel computer using MPL C and C++. He also combined OSA90/hope a commercially available microwave CAD program with a 2D-TLM simulation module for geometry optimization using the Datapipe technique of OSA90/hope. Recently he has developed a distributed client-server computing technique for the TLM method this technique could accelerate the TLM simulation by more than an order of magnitude. Channabasappa Eswarappa received the M.Tech. degree in electrical engineering from the Indian Institute of Technology Kanpur India in 1983 and Ph. D. degree from the University of Ottawa Canada in 1990. He worked as an Assistant Executive Engineer and later as

This paper describes the implementation of transmission-line matrix (TLM) method algorithms on a massively parallel computer (DECmpp 12000), the technique of distributed computing in the UNIX environment, and the combination of TLM analysis with Prony's method as well as with autoregressive moving average (ARMA) digital signal processing for electromagnetic field modelling. By combining these advanced computation techniques, typical electromagnetic field modelling of microwave structures by TLM analysis can be accelerated by a few orders of magnitude.

关键词： Mathematical models

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COMPUTER-AIDED MANUFACTURING OF advanced MICROWAVE moduleS

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INTERNATIONAL JOURNAL OF MICROWAVE AND MILLIMETER-WAVE COMPUTER-AIDED ENGINEERING 1991年第1期1卷 90-111页

作者： PAVIO, AM PAVIO, JS CHAPMAN, JE BOGGAN, GH Texas Instruments Incorporated P.O. Box 655474 Dallas. Texas 75265 Jeanne Pavio is the Manager of the Microwave Advanced Packaging Group at Texas Instruments where she has been cmployed since 1980. She received the BA degree in 1971 and the MS in 1972 both from the University of Connecticut. Her experience base has included the fabrication and assembly of thick and thin film hybrids. At the Texas Instruments Hybrid Microelectronics Laboratory Jeanne implemented nitrogenfireable thick film for ceramic application in surface-mount technology and hybrids. For the last six years she has focused on the automated assembly and packaging of GaAs Monolithic Microwave Integrated Circuits and devices. This has encompassed development of fluxless furnace reflow and void-free vacuum reflow of GaAs components as well as development of automated wirebonding to GaAs Microwave Hybrids. She was instrumental in directly applying this technology to active phased array module production. Her efforts presently involve the implementation of high-volume techniques and automation for insertion of MMIC technology in a cost-effective highvolume environment. She has authored numerous papers involving hybrid fabrication and assembly technology and in particular involving automated assembly and packaging of GaAs MMIC devices. James E. Chapman Jr. was born in Dallas Texas in 1943. He received the BS and MS degrees in Electrical Engineering from Southern Methodist University (SMU) in 1966 and 1968 respectively. During this time he was associated with the Semiconductor Group of Texas Instruments Incorporated as an undergraduate engineering cooperative student working with various silicon products and processes. Mr. Chapman is currently a Senior Member of the Technical Staff assigned to the Microwave Technology and Products Division of the Defense Systems and Electronics Group. In this position he is currently technical director of the Technology Development for Solid-state Phased-Arrays (TDSSPA) Program. This program is a task-ordere

The application of computer-aided manufacturing (CAM) techniques to the assembly and test of a low-cost, high-volume X-band Radar T/R module will be investigated by highlighting the differences between low frequency and microwave CAM methods, focusing on the difficulties of automated testing, evaluation, and circuit tuning. The problems encountered when implementing high-precision automated assembly and test methods, which include wire-bonding, soldering, piece-part placement, thin wafer GaAs probing, and a novel implementation of a microwave circuit laser-tuning technique will also be discussed. These CAM techniques, combined with integrated MMIC technology, are then used to illustrate a manufacturing philosophy targeted toward high-volume microwave module production.

关键词： Microwave devices

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