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作者： Singh, Nageshwar Patel, Hemant K. Dixit, S.K. Vora, H.S. Magnetic and Superconducting Materials Section Materials Advanced Accelerator Sciences Division Raja Ramanna Centre for Advanced Technology Indore - 452013 M.P. India Cryo-engineering and Cryo-module Development Section Raja Ramanna Centre for Advanced Technology Indore - 452013 M.P. India Laser Systems Engineering Section Raja Ramanna Centre for Advanced Technology Indore - 452013 M.P. India Laser Engineering Support Division Raja Ramanna Centre for Advanced Technology Indore - 452013 M.P. India

In this paper, a new dye cell for transverse pumping was designed, modeled, and its performance in a narrow spectral width dispersive resonator, pumped by a high repetition rate copper vapor laser, was investigated. The scheme essentially involves the profiling of the cubical glass and stainless steel cylindrical surface such that convex-plano contour be present near the optical pumping region. The design is an amalgamation of straight and curved periphery to enhance the dye solution flow stabilities near the dye laser axis. A computational fluid dynamics analysis of the liquid flow through this dye cell has been carried out. The dye laser outputs such as optical average power, spectral width and wavelength stability, tuning range, pulse shape, through this new dye cell was evaluated. The dye laser average power about 30 mW was fairly steady over the observation period of more than an hour. The dye laser short-term (1 min) spectral width was within 0.824 ± 0.075 GHz, while, in a long-term, more than an hour, drifted by about 180 MHz. The dye laser wavelength in short-term fluctuates within ±0.0065 nm whereas in a long-term, more than an hour, drifted by about 0.0105 nm. The dye laser tuning range was 10 nm with a sub GHz spectral width operation. The pulse shape of the dye laser follows the pump laser pulse profile. Thus, the dye laser has demonstrated fairly long-term stability, without the use of either low expansion material or close loop control on the output. © 2012 American Institute of Physics.

关键词： Dye lasers

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Influences of etcher chamber condition on critical-dimension shifts in advanced floating gate etching process

Influences of etcher chamber condition on critical-dimension...

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IEEE/SEMI Conference and Workshop on advanced Semiconductor Manufacturing

作者： Sheng-Yuan Chang Yu-Chung Chen An Chyi Wei Hong-Ji Lee Nan-Tzu Lian Tahone Yang Kuang-Chao Chen Chih-Yuan Lu Technology Development Center Advanced Module Process Development Division Macronix International Company Limited Hsinchu Taiwan

The authors investigated the correlation between variation of post-etch critical dimension (ECD) and etcher chamber condition during floating gate etching process. This paper presents the significantly effective method of utilizing the SF 6 /O 2 -based very long plasma-chamber cleaning or the novel Transformer coupled plasma (TCP) window temperature design not only achieves a stable gate CD (CD variation

关键词： Etching Cleaning Nonvolatile memory Logic gates Plasma temperature Polymers

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A self-aligned double patterning technology using TiN as the sidewall spacer

A self-aligned double patterning technology using TiN as the...

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IEEE/SEMI Conference and Workshop on advanced Semiconductor Manufacturing

作者： Yuan-Chieh Chiu Shu-Sheng Yu Fang-Hao Hsu Hong-Ji Lee Nan-Tzu Lian Tahone Yang Kuang-Chao Chen Chih-Yuan Lu Technology Development Center Advanced Module Process Development Division Macronix International Company Limited Hsinchu Taiwan

The TiN was conventionally used as barrier layers for both tungsten plug and AlCu metal lines. This paper reveals a novel back end of line (BEOL) self-aligned double patterning (SADP) technology, which applied TiN as a spacer material. The relative processes are introduced and discussed in detail. The new SADP approach was further applied for Cu damascene structure constructions in the advanced non-volatile memory (NVM).

关键词： Tin Silicon compounds Materials Plasmas Lithography Flash memory

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Post etch killer defect characterization and reduction in a self-aligned double patterning technology

Post etch killer defect characterization and reduction in a ...

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IEEE/SEMI Conference and Workshop on advanced Semiconductor Manufacturing

作者： Hong-Ji Lee Sun-Yi Lin I-Ting Lin Kuo-Liang Wei Sheng-Yuan Chang Nan-Tzu Lian Tahone Yang Kuang-Chao Chen Chih-Yuan Lu Technology Development Center Advanced Module Process Development Division Macronix International Company Limited Hsinchu Taiwan

This paper identifies post etch killer defects, e.g., core bridging, small particle and tiny bridging, and investigates the possible solutions in a SADP module. Among the killer defect adders, core bridging and small particle are commonly observed after the oxide core removal by BOE. Core bridging adder is a carbon-containing polymeric by-product during nitride spacer open; by introducing additional diluted HF (DHF) treatment could effectively eliminate such bridging adder. Small particle adder is found to peel from the poly-Si hard mask-1 (HM1) damaged location, where is eroded during the wafer backside cleaning. It is useful for suppressing the formation of small particle by skipping the wafer backside cleaning process. Tiny bridging adder is block of etched poly-Si HM1 causing short between lines. One possibility of blocked etch adder creating is the fine micromasking formed on the opening of BARC during poly-Si HM1 etching. The effective suppression of tiny bridging adder is using high energetic F-/O-radicals to break through the micromasking in the poly-Si HM1 patterning. The reductions of above killer defects successfully boost up the sorting yield in our 45 nm charge-trapping flash memory.

关键词： Adders Etching Plasmas Cleaning Flash memory Inspection Polymers

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advanced floating gate CD uniformity control in the 75nm node NOR flash memory

Advanced floating gate CD uniformity control in the 75nm nod...

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IEEE/SEMI Conference and Workshop on advanced Semiconductor Manufacturing

This paper describes the advanced control technology of critical dimension uniformity (CDU) by flash gate stack etch process. We have investigated the effective way of utilizing Tri-layer approach, which not only reduces the influence of topology step-height but also improves the range of ECD within die from 17.6nm to 4.9nm. Moreover, the influence of Etcher design on ECD variation becomes larger as the cell transistor size becomes smaller. The etch chamber effect is minimized by developing CF 4 /CHF 3 /N 2 plasma at 15mTorr pressure that provides better ECD uniformity within wafer.

关键词： Plasmas Logic gates Etching Polymers Flash memory Chemistry

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Yield enhancement using source/drain BF2+ implant process optimization

Yield enhancement using source/drain BF2+ implant process op...

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IEEE/SEMI Conference and Workshop on advanced Semiconductor Manufacturing

作者： Tuung Luoh Sheng-Hui Hsieh Chen-Ling Lee Hong Ji Lee Kuo-Liang Wei Chin-Ta Su Ling-Wu Yang Tahone Yang Kuang-Chao Chen Chih-Yuan Lu Technology Development Center Advanced Module Process Development Division Macronix International Company Limited Hsinchu Taiwan

This investigation employs an optimized method to alleviate defects occurring at BF 2 + implanted source/drain areas, some white spots defects found at scribes lines after BPSG (boron and phosphorus doped silicon glass) anneal. The results of physical failure analysis indicate the white spot defects are relative to outgassed fluorine that can't be released out during BPSG thermal annealing. Various approaches which includes changing the stress of post cap layer, lowering down the BF 2 + implant doping concentration, and optimizing the ramp-up speed of post-annealing are all able to alleviate the generation of white spot defects. The optimized process with an additional RTP (rapid thermal annealing) right after BF 2 + implantation delivers 7% yield improvement.

关键词： Implants Annealing Films Delamination Doping Furnaces Silicon

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Reduction of shorts between word lines on charge-trapping flash cell in a self-aligned double patterning technology

Reduction of shorts between word lines on charge-trapping fl...

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IEEE/SEMI Conference and Workshop on advanced Semiconductor Manufacturing

作者： Hong-Ji Lee Kuo-Liang Wei Nan-Tzu Lian Tahone Yang Kuang-Chao Chen Chih-Yuan Lu Technology Development Center Advanced Module Process Development Division Macronix International Company Limited Hsinchu Taiwan

This paper presents a unique gate structure for reducing shorts between word lines on charge-trapping flash cell memory. In the early stage of developing sub-45 nm half-pitch word line by a self-aligned double patterning (SADP) technology, the cell array suffered from abnormal intrinsic word line-to-word line shorts, ca. 96.3% of the bridge rate on the 72 Mb cell memory, due to the formation of polysilicon residues called stringers. The increase of polysilicon over-etching to eliminate stringers involves a trade-off between the removal efficiency of stringers and the feature size maintenance. Hence, a novel bottle-shaped gate profile was tailor-made and studied. As a result, the bridge rates are dramatically suppressed to 0%~10% on the low-density flash cells and ca. 22% in average on the high-density 512 Mb flash cell memory. The novel bottle-shaped gate structure is successfully implemented in advanced charge-trapping flash memory development.

关键词： Logic gates Bridges Flash memory Arrays Etching Films Resists

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Robust shallow trench isolation technique used for 75nm nor flash memory

Robust shallow trench isolation technique used for 75nm nor ...

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IEEE/SEMI Conference and Workshop on advanced Semiconductor Manufacturing

作者： Jeng-Hwa Liao Kuo-Liang Wei Hong-Ji Lee Chun-Min Cheng Chun-Ling Chiang Jung-Yu Hsieh Ling-Wu Yang Tahone Yang Kuang-Chao Chen Chih-Yuan Lu Technology Development Center Advanced Module Process Development Division Macronix International Company Limited Hsinchu Taiwan

We have developed a new Self-aligned poly (SAP) process to improve the tunnel oxide integrity by optimizing the shallow trench isolation (STI) corner rounding profile and reducing the local oxide thinning effect. It is found that double in-situ steam generation (ISSG) liner oxides can effectively improve the STI corner rounding. As for the local oxide thinning effect, the composite pad dielectrics (C-Pad) composed of SiO 2 /poly-Si are good to prevent local thinning of tunnel oxide at STI corner. Moreover, using ISSG tunnel oxide can further reduce the local oxide thinning effect. Excellent breakdown characteristics of tunnel oxide by optimizing the key technologies have been verified in this work.

关键词： Furnaces Oxidation Electric breakdown Silicon compounds Reliability Flash memory Dielectrics

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Etch defect characterization and reduction in hard-mask-based Al interconnect etching

International Journal of Plasma Science and Engineering

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International Journal of Plasma Science and Engineering 2008年第1期2008卷 1-5页

作者： Lee, Hong-Ji Hung, Che-Lun Leng, Chia-Hao Lian, Nan-Tzu Young, Ling-Wu Yang, Tahone Chen, Kuang-Chao Lu, Chih-Yuan Advanced Module Process Development Division Technology Development Center Macronix International Company Ltd. Li-Hsin Road Hsinchu 300 Taiwan

This paper identifies the defect adders, for example, post hard-mask etch residue, post metal etch residue, and blocked etch metal island and investigates the removal characteristics of these defects within the oxide-masked Al etching process sequence. Post hard-mask etch residue containing C atom is related to the hardening of photoresist after the conventional post-RIE ashing at 275C. An in situ O2 -based plasma ashing on RIE etcher was developed to prevent the photoresist hardening from the high-ashing temperature;followed wet stripping could successfully eliminate such hardened polymeric residue. Post metal etch residue was caused from the attack of the Al sidewall by Cl atoms, and too much CHF3 addition in the Al main etch step passivated the surface of Al resulting in poor capability to remove the Al-containing residue. The lower addition of CHF3 in the Al main etch step would benefit from the residue removal. One possibility of blocked etch metal island creating was due to the micromasking formed on the opening of TiN during the hard-mask patterning. We report that an additional TiN surface pretreatment with the Ar/CHF3 /N2 plasmas could reduce the impact of the micromasking residues on blocked metal etch.

关键词： Photoresists

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Production worthy 3D interconnect technology

Production worthy 3D interconnect technology

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2008 3rd International Microsystems, Packaging, Assembly and Circuits technology Conference, IMPACT 2008

作者： Chiou, W.C. Yu, C.H. Advanced Module Technology Division R and D Taiwan Semiconductor Manufacturing Company No.8 Li-Hsin Rd. VI Science Based Industrial Park Hsinchu 300 Taiwan

ISBN: (纸本)9781424436248

In accordance with continuing push for smaller and faster electronics, there is strong demand for further miniaturization and higher performance of mobile and other digital devices. Three- dimensional interconnect with through silicon via is the most potential solution to extend Moore's Law. In recent years, 3D interconnect(3DIC) technology is attracting the interest of university, research institutes, Fab engineers, package engineers, chip designers and equipment manufacturers turn to 3D research and development efforts. It has the potential to be the mainstream for chip manufacturing of in the near future. This technology had the benefits of cost, performance, form factor and heterogeneous integration for chips manufacturing. But thermal dissipation, process technology and infrastructure readiness still are the top three issues for success of 3DIC. Cost and manufacturability will be the key knob to enable this technology. In this paper, we demonstrated a production worthy 3DIC technology with IC Fab infrastructure. Key modules' process and electrical results are reported. Well-controlled high aspect ratio (AR=8:1 and AR=15:1) through silicon vias (TSVs) were successfully filled with both copper (Cu) and tungsten (W). Metal to metal diffusion bonding was demonstrated with good uniformity. For the first time, a cost effective wafer thinning without decreasing effective area by a proprietary process is described. Chains were formed between two wafers through bonded copper structures and electrically probed on the top wafer which had been thinned. Yielding 20K through silicon vias with aspect ratio of 15:1 and resistance of through silicon via chain are demonstrated. © 2008 IEEE.

关键词： Cost effectiveness

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