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检索条件"机构=Advanced Module Technology Division"

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BEOL process integration of 65nm Cu/low k interconnects

BEOL process integration of 65nm Cu/low k interconnects

引用

IEEE International Conference on Interconnect technology

作者： C.C. Jeng W.K. Wan H.H. Lin Ming-Shuo Liang K.H. Tang I.C. Kao H.C. Lo K.S. Chi T.C. Huang C.H. Yao C.C. Lin M.D. Lei C.C. Hsia Mong-Song Liang Advanced Module Technology Division Taiwan Semiconductor Manufacturing Company Limited Hsinchu Taiwan

The process development, characterization and performance evaluation of low-k dielectrics to form multi-level Cu interconnects for the 65 nm CMOS technology node are presented. Significant modifications and improvements over 90nm node have been implemented to overcome those challenges as design rules shrink, which include top via corner rounding control for the robust EM/SM reliability, and inline e-beam inspection for via/trench processes optimization. An in-house developed ECP additive "Trameca" for good Cu gap filling and a controllable hump height for good CMP performance are adopted to achieve tight Rs distributions. The facts that 100% yields of 2.1 millions via chain structure and open/short free on 5m long comb/meander structures along with SM/EM meeting the spec all demonstrated the technology to be a highly manufacturable BEOL process for 65 nm technology node.

关键词： Etching Dielectric materials Packaging Conducting materials CMOS technology Degradation Materials testing Composite materials Semiconductor device manufacture Manufacturing industries

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High performance Cu interconnects capped with full-coverage ALD TaNx layer for Cu/low-k (k/spl sim/2.5) metallization

High performance Cu interconnects capped with full-coverage ...

引用

IEEE International Conference on Interconnect technology

作者： Hsien-Ming Lee J.C. Lin C.H. Peng S.C. Pan C.L. Huang L.L. Su C.H. Hsieh W.S. Shue M.S. LIang Advanced Module Technology Division Taiwan Semiconductor Manufacturing Company Limited Hsinchu Taiwan

Performance of Cu dual damascene interconnects with a full coverage ALD TaNx cap layer coating on the top surface of Cu line has been investigated. With deposition process that generates different ALD TaNx film properties on Cu and low-k dielectrics, 100% yield of line-to-line leakage can be achieved. ALD TaNx cap layer can improve electromigration lifetime by more than 3 times due to improvement of the interface between Cu and cap layer which actually suppress the Cu surface migration without degradation of stress migration performance. This work demonstrates that ALD TaNx cap layer can be successfully integrated with Cu/low-k (k/spl sim/2.5) metallization with potential5% reduction in RC delay as compared to conventional cap layer.

关键词： Metallization Electromigration Testing Delay Atomic layer deposition Adhesives Dielectric substrates Transmission electron microscopy Leakage current Coatings

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Direct determination of interface and bulk traps in stacked HfO/sub 2/ dielectrics using charge pumping method

Direct determination of interface and bulk traps in stacked ...

引用

Annual International Symposium on Reliability Physics

作者： T.H. Hou M.F. Wang K.L. Mai Y.M. Lin M.H. Yang L.G. Yao Y. Jin S.C. Chen M.S. Liang Advanced Module Technology Division Research & Development Taiwan Semiconductor Manufacturing Company Limited Taiwan

For the first time, trap density at SiO/sub 2//Si interface, HfO/sub 2//SiO/sub 2/ interface, and HfO/sub 2/ bulk of stacked HfO/sub 2//SiO/sub 2/ dielectrics are quantified respectively with a simple charge pumping method. It was found that the amount of each individual type of traps can be well correlated to specific process conditions as well as device performance, which makes such innovative characterization method very powerful for process optimization of high-k dielectrics.

关键词： Hafnium oxide Charge pumps High-K gate dielectrics High K dielectric materials MOS devices Electron mobility Electron traps Niobium Frequency measurement Voltage

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High performance Cu interconnects capped with full-coverage ALD TaNx layer for Cu/Low-k (k∼2.5) metallization

High performance Cu interconnects capped with full-coverage ...

引用

Proceedings of the IEEE 2004 International Interconnect technology Conference

作者： Lee, Hsien-Ming Lin, J.C. Peng, C.H. Pan, S.C. Huang, C.L. Su, L.L. Hsieh, C.H. Shue, Winston S. Liang, M.S. Advanced Module Technology Division Taiwan Semiconduct. Mfg. Co. Ltd. Science-Based Industrial Park 8 Li-Hsin 6th Rd. Hsin-Chu 300 Taiwan

ISBN: (纸本)0780383087

Performance of Cu dual damascene interconnects with a full coverage ALD TaNx cap layer coating on the top surface of Cu line has been investigated. With deposition process that generates different ALD TaNx film properties on Cu and low-k dielectrics, 100% yield of line-to-line leakage can be achieved. ALD TaNx cap layer can improves electromigration lifetime by more than 3 times due to improvement of the interface between Cu and cap layer which actually suppresses the Cu surface migration without degradation of stress migration performance. This work demonstrates that ALD TaNx cap layer can be successfully integrated with Cu/low-k(k∼2.5) metallization with potential 5% reduction in RC delay as compared to conventional cap layer.

关键词： Copper

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Low k damage control & its reliability for organic hybrid dual damascene

Low k damage control & its reliability for organic hybrid du...

引用

International Symposium on Physical & Failure Analysis of Integrated Circuits

作者： Y.N. Su J.H. Shieh P.F. Hsu K.C. Lin W.C. Chiou H.H. Kuo H.J. Tao M.S. Liang Advanced Module Technology Division Research and Development Taiwan Semiconductor Manufacturing Company Limited Hsinchu Taiwan

A hybrid dual damascene interconnect approach with organic ultra-low-k for gap filling has been demonstrated. The traditional PR approach with via-first process for dual damascene suffers from ashing damage for CVD ultra-low-k. Our approach is able to circumvent the issues mentioned above without introducing process complication. Good sheet resistance control is obtained for trench etch without a middle stop layer. And good via resistance yield with good thermal stability is obtained as well. 21% of RC product reduction is obtained when it is compared with the PR approach for CVD ultra-low-k.

关键词： Etching Ash Dielectric materials Planarization Leakage current Research and development Semiconductor device manufacture Manufacturing industries Filling Thermal stability

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Reliability robustness of 65nm BEOL Cu damascene interconnects using porous CVD low-k dielectrics with k = 2.2

Reliability robustness of 65nm BEOL Cu damascene interconnec...

引用

Symposium on VLSI technology

作者： K.C. Lin Y.C. Lu L.P. Li B.T. Chen H.L. Chang H.H. Lu S.M. Jeng S.M. Jang M.S. Liang Advanced Module Technology Division Research & Development Taiwan Semiconductor Manufacturing Company Limited Hsinchu Taiwan

ISBN: (纸本)0780382897

Reliability concerns over the applications of porous low-k dielectrics for Cu dual damascene (DD) interconnects have been dismissed with novel film formation methods, patterning approaches and structure designs. Results showed that the BEOL time dependent dielectric breakdown (BEOL TDDB) performance of interconnects built using porous CVD LK's with k=2.2 and pore size /spl sim/2.8nm were not comprised with film pore integrity retained to have TDDB T/sub 63/ predicted to be 1 /spl times/ 10/sup 9/ yrs at 0.3 MV/cm and 125/spl deg/C. Further investigations also revealed that the impacts of weak mechanical and poor thermal properties associated with the LK material on its interconnect electromigration and stress migration performances can be demolished through various interface engineering with EM lifetimes of 0.12 /spl mu/m Cu lines or 0.13 /spl mu/m vias at 1 MA/cm/sup 2/ and 110/spl deg/C longer than 400k hrs or 150k hrs, and SM failure rate = 0 (>100% Re shift) for vias on all test structures after thermal annealing at 150/spl deg/C for 500 hrs.

关键词： Robustness Thermal stresses Thermal engineering Dielectric breakdown Mechanical factors Electromigration Performance evaluation Samarium Life testing Materials testing

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Numerical characterization of the stress induced voiding inside via of various Cu/low k interconnects

Numerical characterization of the stress induced voiding ins...

引用

IEEE International Conference on Interconnect technology

作者： C.H. Yao T.C. Huang K.S. Chi W.K. Wan H.H. Lin C.C. Hsia M.S. Liang Advanced Module Technology Division R & D Taiwan Semiconductor Manufacturing Company Limited Hsinchu Taiwan

Modelling methodologies including a dynamic stress evolution are proposed in this work to characterize the relative stress-induced voiding (SIV) probability inside via of various Cu/low k interconnects. Seven patterns being representative of versatile IC design units are selected. It is demonstrated that our modelling approach can serve as a good method identifying the most troublesome layout units to inside-via SIV, and the results aligned well with the experimental data. From our studies, two kinds of layout styles when designed together are found detrimental: (1) the layout units with via(s) subjected to significant upper-metal edge confinement and (2) the one with via close to big vacancy sources.

关键词： Integrated circuit interconnections Thermal stresses Circuit testing Joining processes Tin Circuit synthesis Numerical simulation Geometry Passivation Thermal resistance

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BEOL process integration of 65 nm Cu/low k interconnects

BEOL process integration of 65 nm Cu/low k interconnects

引用

Proceedings of the IEEE 2004 International Interconnect technology Conference

作者： Jeng, C.C. Wan, W.K. Lin, H.H. Liang, Ming-Shuo Tang, K.H. Kao, I.C. Lo, H.C. Chi, K.S. Huang, T.C. Yao, C.H. Lin, C.C. Lei, M.D. Hsia, Chin C. Liang, Mong-Song Advanced Module Technology Division Taiwan Semiconduct. Mfg. Co. L. Science-Based Industrial Park No. 6 Li-Hsin Rd. 6 Hsin-Chu 300-77 Taiwan

ISBN: (纸本)0780383087

The process development, characterization and performance evaluation of low-k dielectrics to form multi-level Cu interconnects for the 65 nm CMOS technology node are presented. Significant modifications and improvements over 90 nm node have been implemented to overcome those challenges as design rules shrink, which include top via corner rounding control for the robust EM/SM reliability, and inline e-beam inspection for via/trench process optimization. An in-house developed ECP additive "Trameca" for good Cu gap filling and a controllable hump height for good CMP performance are adopted to achieve tight Rs distributions. The facts that 100% yield of 2.1 millions via chain structure and open/short free on 5m long comb/meander structures along with SM/EM meeting the spec all demonstrated the technology to be a highly manufacturable BEOL process for 65 nm technology node.

关键词： Optical interconnects

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Numerical characterization of the stress induced voiding inside via of various Cu/Low k interconnects

Numerical characterization of the stress induced voiding ins...

引用

Proceedings of the IEEE 2004 International Interconnect technology Conference

作者： Yao, C.H. Huang, T.C. Chi, K.S. Wan, W.K. Lin, H.H. Hsia, Chin C. Liang, M.S. Advanced Module Technology Division Taiwan Semiconduct. Mfg. Co. Ltd. Science-Based Industrial Park No. 6 Li-Hsin Rd. 6 Hsin-Chu 300-77 Taiwan

ISBN: (纸本)0780383087

Modeling methodologies including a dynamic stress evolution are proposed in this work to characterize the relative stress-induced voiding (SIV) probability inside via of various Cu/Low k interconnects. Seven patterns being representative of versatile IC design units are selected. It is demonstrated that our modeling approach can serve as a good method identifying the most troublesome layout units to inside-via SIV, and the results aligned well with the experimental data. From our studies, two kinds of layout styles when designed together are found detrimental: (1) the layout units with via(s) subjected to significant upper-metal edge confinement and (2) the one with via close to big vacancy sources.

关键词： Copper metallurgy

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Challenges in Cu/low-k integration

Challenges in Cu/low-k integration

引用

International Electron Devices Meeting (IEDM)

作者： Mong-Song Liang Advanced Module Technology Division Research and Development Taiwan Semiconductor Manufacturing Company Limited Hsinchu Taiwan

ISBN: (纸本)0780386841

advanced BEOL materials matching in chemical, thermal, and mechanical properties remain a challenge to the industry. New failure modes associated with BEOL reliability hinder the mass production of Cu/low-k technology. With 15% IMD effective-K reduction target, low-K, ESL, and metal pitch/height ratio optimization are crucial. Integrated module built-in reliability robustness is to assure stable production. Physical, electrical, reliability, and manufacturability aspects of individual module require full characterization. Implementations of proper queue-time control and iAPC between modules will minimize excursions and increase process window.

关键词： Capacitive sensors Manufacturing industries Robustness Production Samarium Chemical technology Semiconductor device manufacture Semiconductor materials Chemical industry Dielectrics

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