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检索条件"机构=Advanced Module Technology Division"

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Optimization and scaling limit forecast of nitrided gate oxide using an equivalent nitride/oxide (N/O) stack model

Optimization and scaling limit forecast of nitrided gate oxi...

引用

IEEE International Conference on Integrated Circuit Design and technology (ICICDT)

作者： V.S. Chang C.-C. Chen Y. Jin C.-H. Chen T.-L. Lee S.-C. Chen M.-S. Liang Advanced Module Technology Division Taiwan Semiconductor Manufacturing Co. Ltd. Hsinchu 300 Taiwan

A semi-empirical model was developed to calculate the equivalent oxide thickness (EOT) and leakage current of nitrided gate oxide by hypothetically dividing the nitrided oxide into a nitride/oxide (N/O) stack. The calculations agree well with the experimental data (R/sup 2/ > 0.99) for various nitrided oxides with EOT ranging from 12 to 23 /spl Aring/. A model-based strategy for the optimization of nitrided oxide is presented and demonstrated by a nitrided oxide sample which meets both the EOT and leakage current requirements of ITRS 65-nm low standby power (LSTP) technology and shows no electron mobility degradation. The model forecasts that a nitrogen concentration of 20% approximately the maximum from Oxide nitridation processes - satisfies the ITRS requirements for production until Year 2007. The production afterwards will require alternative dielectrics such as N/O stack or high-k materials for greater leakage current reductions.

关键词： Predictive models Leakage current Nitrogen Degradation High K dielectric materials High-K gate dielectrics Dielectric constant Optimized production technology Electron mobility Metrology

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Extended scaling of ultrathin gate oxynitride toward sub-65nm CMOS by optimization of UV photo-oxidation, soft plasma/thermal nitridation & stress enhancement

Extended scaling of ultrathin gate oxynitride toward sub-65n...

引用

Symposium on VLSI technology

作者： Chi-Chun Chen V.S. Chang Y. Jin C.-H. Chen T.-L. Lee S.-C. Chen M.-S. Liang Advanced Module Technology Division Research & Development Taiwan Semiconductor Manufacturing Co. Ltd. Taiwan

ISBN: (纸本)0780382897

A novel UV photo-oxidation (UVPO) is developed for ideal "atomic-layer oxidation" with excellent thickness control down to 4/spl Aring/, which is very promising for interfacial layer formation of scaled gate oxynitride and high-k applications. In addition, ultrathin oxynitride (EOT<12/spl Aring/) using a newly-developed low ion-energy nitrogen plasma (30% plasma damage reduction) in combination with thermal nitridation is demonstrated for n/pMOSFET performance optimization. Finally, device performance is further enhanced (+7% of nFET Ion-Ioff by tensile stress with negligible impact on pFET) by mechanical stress modulation from strain contact-etch-stop layer (CESL). The proposed technologies represent an efficient approach to realize ultrathin gate oxynitride toward sub-65nm CMOS production.

关键词： Thermal stresses Plasma applications Plasma devices Atomic layer deposition Oxidation Thickness control High K dielectric materials High-K gate dielectrics Nitrogen MOSFET circuits

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Electrochemically induced defects during post Cu CMP cleaning

Electrochemically induced defects during post Cu CMP cleanin...

引用

IEEE International Conference on Interconnect technology

作者： W.C. Chiou Y.H. Chen S.N. Lee S.M. Jeng S.M. Jang M.S. Liang DiElectrical and CMP Department Advanced Module Technology Division Taiwan Semiconductor Manufacturing Company Limited Hsinchu Taiwan

The electrochemical properties of various cleaning reagents of high, medium or low pH values for post Cu CMP cleaning and their interaction mechanisms with Cu surfaces were studied. Results showed that for the Cu in TMAH (pH=11) a reverse reaction, Cu re-deposition, was also observed although the Cu was easier to corrode due to its more negative corrosion potential in this solution. Because of this abnormal Cu re-deposition, Cu anode and cathode reactions were found to occur at the same Cu islands, where the Cu were corroded and then re-filled by re-deposition to form allow defects. These defects were extremely difficult to detect by in-line defect inspection tools during wafer processing and can only be identified by FA after WAT failures. Careful examinations of electrochemical properties revealed that hump in the I-V curve is the key to this abnormalities and a novel solution was proposed and developed to eliminate these defects.

关键词： Cleaning Copper Corrosion Chemical technology Chemical processes Dielectrics Abrasives Anodes Cathodes Inspection

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Robust low-k film (k=2.1/spl sim/2.5) for 90/65 nm BEOL technology using bilayer film schemes

Robust low-k film (k=2.1/spl sim/2.5) for 90/65 nm BEOL tech...

引用

IEEE International Conference on Interconnect technology

作者： H.L. Chang Y.C. Lu L.P. Li B.T. Chen K.C. Lin S.M. Jeng S.M. Jang M.S. Liang Department of DiElectrical and CMP Advanced Module Technology Division Research & Development Taiwan Semiconductor Manufacturing Company Limited Hsinchu Taiwan

Cu/porous low-k (PLK) with k/spl les/2.5 is the current choice to 65nm and beyond BEOL interconnect technologies. However, critical concerns of the weak physical and chemical structures of PLK (k/spl les/2.5) films on their integration compatibilities, such as CMP defectivity and trench bottom/via smoothness, electrical performances, such as etching/ashing film damaging, and reliability performances, such as electromigration (EM), stress migration (SM) and time-dependent dielectric breakdown (TDDB), still challenge their application feasibility. A novel in-situ formed trench-porous (k=2.5) and via-dense (k=2.7) k=2.5/2.7 bilayer film design was proposed in this study to overcome these facing issues. Cu/PLK DD study results showed that CMP defectivity was /spl sim/4/spl times/ improved and trench bottom was smoothened with a k=2.5/2,7 bilayer PLK approach. Electrical performances using this approach also showed that film damaging from DD etching/ashing was reduced with the higher chemical resistance of the via in the bilayer. Reliability study results demonstrated that an /spl sim/ 2000/spl times/ better DD TDDB lifetime was achieved due to smooth trench bottoms. When changing from Cu/k=2.5 single layer to Cu/k=2.5/2.7 bilayer, SM and EM performances were not impacted. Moreover, with >405 improved hardness and film adhesion the bilayer PLK approach highlights a potential direction to improve Cu/k=2.5 PLK manufacturability in packaging. All these results indicate that this Cu/bilayer BEOL interconnection applicable for 65 nm and beyond generation CMOS technologies.

关键词： Robustness Chemical technology Etching Samarium CMOS technology Electromigration Stress Dielectric breakdown Electric resistance Adhesives

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Investigation of plasma-induced damage of nickel mono-silicide in semiconductor manufacturing

Investigation of plasma-induced damage of nickel mono-silici...

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International Symposium on Physical & Failure Analysis of Integrated Circuits

作者： P.F. Hsu M.H. Tsai B.C. Perng J.H. Shieh H.J. Tao M.S. Liang Advanced Module Technology Division Taiwan Semiconductor Manufacturing Company Ltd Taiwan Adv. Module Technol. Div. Taiwan Semicond. Manuf. Co. Ltd. Taiwan

In this paper, we studied the plasma-induced damage of a nickel mono-silicide (NiSi) using XPS, TEM, AES and SIMS. According to the previous experience, it suggests that NiSi is easily oxidized when O/sub 2/ exists in plasma, which results in a high sheet resistance of oxide/silicide (NiSiO/sub x/) mixture. A substrate-dependent oxidation of NiSi formed on the different dose-implanted silicon or poly-silicon substrate was also investigated in this study.

关键词： Plasma materials processing Nickel Semiconductor device manufacture Silicides Plasma applications Oxidation Substrates Plasma temperature Silicon Silicidation

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Effects of base oxide in HfSiO/SiO/sub 2/ high-k gate stacks

Effects of base oxide in HfSiO/SiO/sub 2/ high-k gate stacks

引用

International Symposium on Physical & Failure Analysis of Integrated Circuits

作者： W.H. Wu M.C. Chen M.F. Wang T.H. Hou L.G. Yao Y. Jin S.C. Chen M.S. Liang Department of Electronics Engineering National Chiao Tung University Hsinchu Taiwan Advanced Module Technology Division Taiwan Semiconductor Manufacturing Company Limited Hsinchu Taiwan

The electrical characteristics of HfSiO/SiO/sub 2/ high-k gate stacks have been extensively explored with regard to the effects of base oxide. The flatband voltage shift in N/PMOS capacitors is independent of base oxide thickness, and the dielectric breakdown of the gate stacks is determined by base oxide. In addition, base oxide thickness has a great impact on device performance and charge trapping, presumably due to remote Coulomb scattering (RCS) in the HfSiO bulk layer and direct tunneling through the base oxide. Threshold voltage instability induced by charge trapping will be a major reliability concern for Hf-based high-k gate dielectrics in the future.

关键词： High K dielectric materials High-K gate dielectrics Breakdown voltage Capacitors Dielectric breakdown Tunneling Leakage current Electric variables Capacitance-voltage characteristics Industrial electronics

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Noise coupling to signal trace and via from power/ground simultaneous switching noise in high speed double data rates memory module

Noise coupling to signal trace and via from power/ground sim...

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IEEE International Symposium on Electromagnetic Compatibility (EMC)

作者： Jongbae Park Hyungsoo Kim Jun So Pak Youchul Jeong Seungyong Baek Joungho Kim Jung-Joon Lee Jae-Joon Lee Terahertz Interconnection and Package Laboratory Department of EECS Korea Advanced Institute of Science and Technology Daejeon South Korea Module Design Group Memory Division Samsung Electronics Company Limited South Korea

ISBN: (纸本)0780384431

We suggested the model to demonstrate simultaneous switching noise (SSN) coupling to signal and verified experimentally. There are two coupling mechanisms; one is the SSN coupling through the reference changing via, and the other is the SSN coupling through the signal trace. Through measurement and analysis, we confirmed that the worst SSN coupling occurs when strip lines have the signal via changing reference plane with SSN. Furthermore, we demonstrated that the power/ground noise coupling to the signal is reduced by placing the reference changing via at the position where the power/ground cavity impedance is low, or by adjusting the line length between two reference changing vias.

关键词： Impedance Frequency Voltage Strips Noise reduction Power generation Noise generators Signal generators Couplings Packaging

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Spread spectrum clock generator with delay cell array to reduce the EMI from a high-speed digital system

Spread spectrum clock generator with delay cell array to red...

引用

IEEE International Symposium on Electromagnetic Compatibility (EMC)

作者： Jonghoon Kim Dong Gun Kam Joungho Kim Module Design Team Memory Division Device Solution Network Samsung Electronics Company Limited Hwasung Gyeonggi South Korea Department of Electrical Engineering & Computer Science Korea Advanced Institute of Science and Technology Daejeon South Korea

ISBN: (纸本)0780384431

In high-speed digital systems, most of the EMI from the system is caused by high-speed digital clock drivers and synchronized circuits. In order to reduce the EMI from the system clocks, spread spectrum clock (SSC) techniques that modulate the system clock frequency have been proposed. A conventional spread spectrum clock generator with a phase locked loop (SSCG-PLL) has been implemented by controlling period jitter. However, the conventional SSCG-PLL becomes more difficult to implement at higher clock frequencies, in the GHz range, because of the random period jitter of the PLL. Furthermore, the attenuation of EMI is decreased due to the random period jitter of the PLL. To overcome these problems associated with the random period jitter, we propose a spread spectrum clock generator with a delay cell array (SSCG-DCA), which controls the position of clock transitions. Measurement and simulation have demonstrated that the proposed SSCG-DCA is easier to implement and attenuating the EMI is more effective compared with the conventional SSCG-PLL. The proposed SSCG-DCA was implemented on a chip using a 0.35 /spl mu/m CMOS process and a 9 dB attenuation of the EMI was achieved at 390 MHz.

关键词： Spread spectrum communication Clocks Delay Electromagnetic interference Digital systems Jitter Phase locked loops Frequency Attenuation Driver circuits

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advanced 300mm Cu/CVD LK (k=2.2) Multilevel Damascene Integration for 90/65nm Generation BEOL Interconnect Technologies

Advanced 300mm Cu/CVD LK (k=2.2) Multilevel Damascene Integr...

引用

2003 Symposium on VLSI technology

作者： Li, L.P. Lu, Y.C. Lu, H.H. Yang, Y.L. Lin, C.H. Lin, K.C. Chen, B.T. Liang, M. Jang, S.M. Liang, M.S. Advanced Module Technology Division Research and Development Taiwan Semiconduct. Mfg. Company Science-Based Industrial Park Hsin-Chu Taiwan

Nine-metal-level (9ML) Cu/CVD low-k dielectric with k=2.2, Cu/LK (k=2.2), damascene integration on 300mm wafers for 90/65nm generation has been successfully demonstrated for the first time. To minimize line-line capacitance for least BEOL interconnect RC delay, no higherk cap for Cu CMP or higher-k middle etch stop layers for metal trench etching were used in inter metal dielectric (IMD) film stacking. Integration challenges in the Cu/LK (k=2.2) damascene building were overcome by novel approaches in IMD film processing, Cu CMP and patterning. Excellent physical, electrical, reliability, and packaging results from this Cu/LK (k=2.2) BEOL interconnects are demonstrated.

关键词： Large scale systems

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Novel CMP Slurries for Planarization of Multilevel Copper Interconnect

Novel CMP Slurries for Planarization of Multilevel Copper In...

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2003 Symposium on VLSI technology

作者： Song, J.Y. Chen, Y.H. Lee, S.N. Chiou, W.C. Tseng, T.C. Kuo, H.H. Chuang, C.J. Lin, K.C. Jang, S.M. Liang, M.S. Advanced Module Technology Division Taiwan Semiconduct. Mfg. Company No. 6 Li-Hsin Rd. VI Hsinchu Taiwan

Novel slurries were developed for Cu, TaN, and dielectric chemical mechanical polish (CMP) to greatly enhance the planarity of Cu dual damascene interconnect (DDI). Compared with conventional alumina-based slurries, the newly designed polymer-based slurries achieve best sheet resistance (Rs) control over a wide range of Cu density on various stack layers with excellent overpolish window. Through optimizing chemical components, these novel slurries also demonstrated smooth Cu morphology and least galvanic corrosion during polish and robust reliability of eight level Cu interconnect, including electromigration (EM) and stress migration (SM), has been achieved.

关键词： Electric connectors

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