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International Electron Devices Meeting (IEDM)

作者： Z.C. Wu T.J. Chou S.H. Lin Y.L. Huang C.H. Lin L.P. Li B.T. Chen Y.C. Lu C.C. Chiang M.C. Chen W. Chang S.M. Jang M.S. Liang Department of Dielectric and ChP Advanced Module Technology Division R&D Taiwan Semiconductor Manufacturing Company Limited Hsinchu Taiwan Department of Electronics Engineering National Chiao Tung University Hsinchu Taiwan

Successful integration of high performance Cu dual damascene interconnects (DDIs) using a low-k etch stop (LES, oxygen-doped carbide, k/spl sim/3.0) and a porous low-k IMD (OSG, k/spl sim/2.5) has been demonstrated for the first time. The Cu DDIs with the LES not only revealed excellent resistance to stress induced voiding (SIV) but also exhibited 21% better interconnect RC delay, 100% higher via-EM endurance, 100 times lower line-line leakage at 125/spl deg/C, and 5% faster device operation speed as compared to the DDIs with a currently used etch stop (CES, oxygen-doped carbide, k/spl sim/4.5).

关键词： Dielectrics Etching Delay Integrated circuit interconnections Research and development Semiconductor device manufacture Electronics industry Manufacturing industries Industrial electronics Stress

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Leakage and breakdown mechanisms in Cu damascene with a bilayer-structured /spl alpha/-SiCN//spl alpha/-SiC dielectric barrier

Leakage and breakdown mechanisms in Cu damascene with a bila...

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IEEE International Conference on Interconnect technology

作者： Chiu-Chih Chiang I-Hsiu Ko Mao-Chieh Chen Zhen-Cheng Wu Yung-Cheng Lu Syun-Ming Jang Mong-Song Liang Department of Electronics Engineering National Chiao Tung University Hsinchu Taiwan Department of Dielectric and CMP Advanced Module Technology Division R&D Taiwan Semiconductor Manufacturing Company Limited Hsinchu Taiwan

ISBN: (纸本)0780377974

This work investigates the leakage and breakdown mechanisms in the Cu damascene structure with a carbon-doped low-k PECVD organosilicate glass (OSG, k=3) as the intermetal dielectric (IMD) and an /spl alpha/-SiCN(k=5)//spl alpha/-SiC(k=4) bilayer-structured dielectric film as the Cu-cap barrier. It is found that the leakage mechanism between Cu lines is dependent on the thickness ratio of the /spl alpha/-SiCN//spl alpha/-SiC bilayer barrier in the Cu damascene structure. In the Cu damascene using an /spl alpha/-SiCN//spl alpha/-SiC bilayer barrier of 40 nm/10 nm or 30 nm/20 nm bilayer thickness, the large leakage current (Frenkel-Poole emission) between Cu lines is attributed to the plenty of interfacial defects, such as cracks, voids, traps or dangling bonds at the /spl alpha/-SiC/OSG interface, which are generated by the larger tensile force of the thicker /spl alpha/-SiC film. On the other hand, the breakdown field and TDDB (time-dependent-dielectric-breakdown) lifetime of the Cu damascene reveal little dependence on the thickness ratio of the /spl alpha/-SiCN//spl alpha/-SiC bilayer barrier, and the observed breakdown of the Cu damascene structure is presumably due to dielectric breakdown of the bulk OSG layer.

关键词： Dielectric breakdown Copper Leakage current Temperature measurement Semiconductor device breakdown Dielectric films Integrated circuit interconnections Etching Current measurement Thickness measurement

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Direct measurement of gate oxide damage from plasma nitridation process

Direct measurement of gate oxide damage from plasma nitridat...

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International Symposium on Plasma- and Process-Induced Damage

作者： Y. Jin C.-C. Chen V.S. Chang D.-Y. Leel T.-L. Lee S.-C. Chen M.-S. Liang Institute of Electronics National Chiao Tung University Hsinchu Taiwan Advanced Module Technology Division Research & Development Taiwan Semiconductor Manufacture Co. Ltd. Hsin Chu Taiwan R.O.C. Advanced Module Technologv Division Research & Development Taiwan Semiconductor Manufacturing Company Limited Hsinchu Taiwan Institute of Electronics National Chiao Tung University Hsin-Chu Taiwan R.O.C.

Surface voltage (Vsurf) measurements using a non-contact mode measurement (NCMM) tool on bare thick oxide wafers have been widely used for the characterization of plasma charging damage in BEOL processes. In this paper, plasma damage to gate oxide in a plasma nitridation (PN) system has been systematically studied by an NCMM system on bare oxide wafers. The results demonstrate that conventional V/sub surf/ measurement on thick oxide bare wafers has the sensitivity to detect the positive charge induced by the PN process and to characterize the plasma uniformity, but this method might underestimate the damage to gate oxide. It is found that both D/sub it/ and Q/sub tot/ measurements on very thin oxide are more accurate methods to quantify the plasma damage. However, only D/sub it/ correlates well with device performance. The findings of this study provide a time saving and cost effective method for PN process optimization and process monitoring.

关键词： Plasma measurements Thickness measurement Surface charging Voltage measurement Current measurement Charge measurement Q measurement Plasma devices Cost function Optimization methods

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advanced Cu/low-k (k=2.2) multilevel interconnect for 0.10/0.07 /spl mu/m generation

Advanced Cu/low-k (k=2.2) multilevel interconnect for 0.10/0...

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Symposium on VLSI technology

作者： S.M. Jang Y.H. Chen T.J. Chou S.N. Lee C.C. Chen T.C. Tseng B.T. Chen S.Y. Chang C.H. Yu M.S. Liang Advanced Module Technology Division Research and Development Taiwan Semiconductor Manufacturing Company Hsinchu Taiwan

A spin-on dielectric (SOD, k=2.2) has been integrated with Cu for 0.10/0.07 /spl mu/m generations. To minimize interconnect capacitance, conventional CVD cap layer (k=4.5-7.5) is replaced by a SOD dielectric (k=2.9) and no stop layer for trench etch is used for the porous inter-metal dielectric (IMD). The issue of photoresist poisoning is resolved by nitrogen-free IMD processing. Using polymeric abrasive together with polishing parameters designed in a low friction domain for planarization, 6-level Cu/porous SOD multilevel interconnect is demonstrated for the first time. Electrical testing shows promising results for the high-performance dual damascene structure.

关键词： Thermal stresses Etching Resists Tensile stress Silicon carbide Capacitance Testing Curing Dielectric materials Silicon compounds

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A 90 nm generation copper dual damascene technology with ALD TaN barrier

A 90 nm generation copper dual damascene technology with ALD...

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International Electron Devices Meeting (IEDM)

作者： C.H. Peng C.H. Hsieh C.L. Huang J.C. Lin M.H. Tsai M.W. Lin C.L. Chang W.S. Shue M.S. Liang Advanced Module Technology Development Division Research and Development Taiwan Semiconductor Manufacturing Company Limited Hsinchu Taiwan

As the device dimension continues to shrink, the need for a thinner barrier for copper has risen in order to meet the requirements for future device performance. The conventional barrier process by physical vapor deposition (PVD) has the limitation to achieve conformal step coverage across the dual damascene structure , and therefore would face a bottleneck when the thickness reduction is required. In this work, the atomic layer deposition (ALD) technique is applied for the TaN barrier process of a 90 nm generation copper dual damascene integration with low-k dielectrics of k=3.0. The ALD technique could not only provide a conformal step coverage on both trenches and vias, it could also allows reasonable thickness control for thickness of the order of 10 /spl Aring/. The integration results show that ALD TaN has promising electrical performance on sheet resistance, via resistance, and line-to-line leakage, and it also has superior reliability performance on electromigration, stress migration, and bias temperature test as compared with conventional PVD TaN.

关键词： Copper Atherosclerosis Electric resistance Chemical vapor deposition Atomic layer deposition Damascene integration Dielectrics Thickness control Electromigration Stress

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advanced metal barrier free Cu damascene interconnects with PECVD silicon carbide barriers for 90/65-nm BEOL technology

Advanced metal barrier free Cu damascene interconnects with ...

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International Electron Devices Meeting (IEDM)

作者： Z.C. Wu Y.C. Lu C.C. Chiang M.C. Chen B.T. Chen G.J. Wang Y.T. Chen J.L. Huang S.M. Jang M.S. Liang Department of Dielectric and Cmp Advanced Module Technology Division Research and Development Taiwan Semiconductor Manufacturing Company Hsinchu Taiwan Department of Electronics Engineering National Chiao Tung University Hsinchu Taiwan Department of Dielectric and CMF Advanced Module Technology Division Research and Development Taiwan Semiconductor Manufacturing Company Hsinchu Taiwan Department of Dielectric and CMP Advanced Module Technology Division Research and Development Taiwan Semiconductor Manufacturing Company Hsinchu Taiwan

advanced metal barrier free (MBF) Cu dual damascene interconnects (DDIs) have been successfully fabricated using a low-k CVD OSG (k=2.5) and PECVD silicon carbides for the first time. With PECVD silicon carbides replacing TaN, the Cu DDIs thus built showed 8% better in interconnect RC delay, 36% lower in via resistance and three orders of magnitude lower in line-line leakage at 200/spl deg/C. The newly developed technology also enhanced Cu TDDB lifetime by more than three orders of magnitude. On the MBF DDIs, 15%-faster 90-nm CMOS device operation has been achieved, which makes the newly developed MBF Cu DDI technology promising for high performance sub-90 nm CMOS devices and beyond.

关键词： Silicon carbide Delay CMOS technology Atherosclerosis Research and development Semiconductor device manufacture Temperature Acceleration Dielectric breakdown Threshold voltage

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Defect reduction of copper BEOL for advanced ULSI interconnect

Defect reduction of copper BEOL for advanced ULSI interconne...

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IEEE International Conference on Interconnect technology

作者： Hsueh-Chung Chen Teng-Chun Tsai Yi-Min Huang Chao-Hui Huang Chien-Hung Chen Yung-Tsung Wei Ming-Sheng Yang Juan-Yuan Wu Tri-Rung Yew Jen-Kon Chen United Foundry Service United Microelectronics Corporation Limited Hopewell Junction NY USA Advanced Technology Development Department United Microelectronics Corporation Limited Hsinchu Taiwan Division Process Module A Department United Microelectronics Corporation Limited Hsinchu Taiwan

ISBN: (纸本)0780366786

In this paper, a full discussion of the defect reduction in copper BEOL technology of a 1P/3M logic product is presented for the first time. Defectivity is inspected from AEI to CMP on various metal levels. Defectivity is classified into non CMP-related type and CMP-related type. Most of the non-CMP type defects are foreign matter coming from the environment or from the processing residues. They can be effectively removed in a CMP step, as long as they were not trapped in the metal trench. On the other hand, the CMP-related type defects impact the consecutive process and yield significantly. Examples of the killer defects are slurry residues, corrosion, and scratching. Prevention and reduction of defects is discussed. Product yield is greatly improved after the reduction of defectivity.

关键词： Copper Ultra large scale integration Corrosion Slurries Microelectronics Dielectric materials Atherosclerosis Chemical vapor deposition Chemical processes Inspection

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The solder joint and runner metal reliability of wafer-level CSP (Omega-CSP)

The solder joint and runner metal reliability of wafer-level...

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Electronic Components and technology Conference (ECTC)

作者： In-Soo Kang Jong-Heon Kim I.S. Park Ki-Rok Hur Soon-Jin Cho Hun Han Jin Yu Module PKG Team Memory R&D Division Hyundai Electronics Industries Company Limited Incheon South Korea Department of Materials Science &Engineering Korea Advanced Institute of Science and Technology Taejon South Korea

Wafer-level Chip Size Package (Wafer Level CSP)s are competing with normal CSPs because they provide the benefits of real chip size package with low manufacturing cost. However, solder joint and runner metal reliability in board level are still critical to the acceptance of WLCSP as an alternative package. In Hyundai Electronics, Wafer-Level CSP without underfill, called Omega-CSP, has been developed for a high speed DRAM application. Omega CSP has a newly developed dielectric polymer as a stress buffer and modified redistribution process. This work aimed at the assessment of the solder joint reliability characteristics and the runner metal reliability. We studied and examined the reliability in terms of the property of dielectric polymer and the runner structure. According to the results, it was found that solder joint reliability strongly depended on the solder ball size and runner thickness. In addition, the effects of CTE/modulus of dielectric polymer on the reliability solder joint will be discussed.

关键词： Soldering Chip scale packaging Electronics packaging Wafer scale integration Dielectrics Polymers Manufacturing Costs Random access memory Stress

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Embedded waveguide filters for microwave and wireless applications using cofired ceramic technologies

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International Journal of Microcircuits and Electronic Packaging 1998年第3期21卷 279-283页

作者： Gipprich, J. Stevens, D. Hageman, M. Piloto, A. Zaki, K. Rong, Y. Northrop Grumman Corporation Electron. Sensors and Syst. Division P. O. Box 1521 Baltimore MD 21203 United States Electrical Engineering Department University of Maryland College Park MD 20742 United States Northrop Grumman Corporation Baltimore MD United States Johns Hopkins University Northrop Grumman Electron. S. Baltimore MD United States Acad. Aperture Module Eng. Dept. Natl. Technical Committee of IMAPS RF Wireless Microwave Subcommittee Baltimore IEEE AP-MT. Chapter Georgia Institute of Technology Westinghouse Electronic Corporation Baltimore MD United States Active Aperture T/R Module Eng. D. Northrop Grumman's Electron. S. Sys. Devmt. and Operations Division Northrop Grumman Electron. Syst. S. Baltimore MD United States University of Texas Texas Instruments Hybrid Microelectronics Laboratory Advanced Missile Systems Department Ain Shams University Cairo Egypt University of California Berkeley CA United States Department of Electrical Engineering Ain Shams University College Park MD United States Res. Assistant Electron. Res. Lab. University of California Berkeley CA United States Electrical Engineering Department University of Maryland College Park MD United States Department of Electrical Engineering

This paper describes a waveguide filter technology suitable for Cofired Ceramics. The filters employ novel waveguide structures that are realized by printing parallel planar conductors that serve as the top and bottom of the waveguide, connected together with two rows of closely spaced metal filled vias. These filters may be embedded into multilayer ceramics and integrated with other electronic circuitry. A significant feature of the waveguide filter is that it provides lower insertion loss due to its wider conductors. Two different filters designed for X-band frequencies are described and measured performance is presented in this work.

关键词： Microwave filters

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PARALLEL AND DISTRIBUTED TLM COMPUTATION WITH SIGNAL-PROCESSING FOR ELECTROMAGNETIC-FIELD MODELING

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INTERNATIONAL JOURNAL OF NUMERICAL MODELLING-ELECTRONIC NETWORKS DEVICES AND FIELDS 1995年第3-4期8卷 169-185页

作者： SO, PPM ESWARAPPA, C HOEFER, WJR NSERC/MPR Teltech Research Chair in RF Engineering Department of Electrical and Computer Engineering University of Victoria Victoria British Columbia V8W 3P6 Canada Poman So received his B.Sc. degree in computer science and physics from the University of Toronto Toronto Onatario Canada in 1985. He obtained his B.A. Sc. and M.A.Sc. degrees in electrical engineering (summa cum laude) from the University of Ottawa Ottawa Ontario Canada in 1987 and 1989 respectively. Mr So was a research engineer in the University of Ottawa from January 1989 to October 1991 his research interests included CAD techniques of microwave circuits and numerical methods for electromagnetic wave modelling. He specialized in the development of electromagnetic engineering CAD software and successfully implemented a number of electromagnetic wave simulators based on the two-dimensional and three-dimensional transmission-line matrix methods. From August 1990 to February 1991 he accompanied Professor W. J. R. Hoefer to Rome Italy and Sophia Antiopolas France. During that time he implemented a parallel version of the 3D-TLM simulator for the CM-2 Connection Machine using C-Star and X Windows Library. He is a research engineer and a Ph.D. student at the University of Victoria Victoria British Columbia Canada. He ported the 2D- and 3D-TLM simulators to DECmpp 1200 massively parallel computer using MPL C and C++. He also combined OSA90/hope a commercially available microwave CAD program with a 2D-TLM simulation module for geometry optimization using the Datapipe technique of OSA90/hope. Recently he has developed a distributed client-server computing technique for the TLM method this technique could accelerate the TLM simulation by more than an order of magnitude. Channabasappa Eswarappa received the M.Tech. degree in electrical engineering from the Indian Institute of Technology Kanpur India in 1983 and Ph. D. degree from the University of Ottawa Canada in 1990. He worked as an Assistant Executive Engineer and later as

This paper describes the implementation of transmission-line matrix (TLM) method algorithms on a massively parallel computer (DECmpp 12000), the technique of distributed computing in the UNIX environment, and the combination of TLM analysis with Prony's method as well as with autoregressive moving average (ARMA) digital signal processing for electromagnetic field modelling. By combining these advanced computation techniques, typical electromagnetic field modelling of microwave structures by TLM analysis can be accelerated by a few orders of magnitude.

关键词： Mathematical models

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