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IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

作者： Shin-En Wu G.P. Li Advanced Semiconductor Device Research Laboratory Department of Electrical & Computer Engineering University of California Irvine CA USA

The authors present an alternative thin-film SOI (silicon-on-insulator) design that achieves low source-substrate injection efficiency to enable device operation at 5-V drain bias without transistor latch or anomalous breakdown. As an alternative to LDD (lightly doped drain) implants, two relatively simple alterations to the conventional SOI MOSFET were incorporated. Two features in the proposed structure distinguish it from past thin-film SOI designs: salicide source/drain electrodes that extend fully to the insulating material and complete gate overlapping of source/drain implants. The effectiveness of the proposed design in prohibiting the parasitic bipolar action from becoming catastrophic is shown. The simulated output characteristic reveals a breakdown voltage approaching 7 V for the transistor, a significant improvement over the result reported by G.A. Armstrong et al. (1991).< >

关键词： MOSFETs Implants Electrodes Electric breakdown Thin film transistors Degradation Semiconductor devices Laboratories Semiconductor device breakdown Bipolar transistors

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Efficient test generation for built-in self-test boundary-scan template

Efficient test generation for built-in self-test boundary-sc...

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VLSI Test Symposium

作者： P. Nagvajara M.G. Karpovsky L.B. Levitin Department of Electrical and Computer Engineering Drexel University Philadelphia PA USA Research Laboratory for Design and Testing of Computer and Communication Systems Department of Electrical Computer and System Engineering Boston University Boston MA USA

An analysis and design of a pseudorandom pattern generator, (PRPG), based on a linear recurrence, for built-in self-test (BIST) boundary scan design is presented. The authors present for the case when r>or=s, a design of an s-stage PRPG capable of producing 2/sup s/-1 distinct r-bit patterns within 2/sup s/-1 clock pulses independent of the hardware realization of the PRPG. For the case when r >

关键词： Automatic testing Built-in self-test Circuit testing Clocks Test pattern generators Pulse generation Pattern analysis Laboratories System testing Design engineering

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Physics-Based Design and Yield Optimization of MMICs

Physics-Based Design and Yield Optimization of MMICs

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European Conference on Microwave

作者： J.W. Bandler Q. Cai R.M. Biernacki S.H. Chen Q.J. Zhang Simulation Optimization Systems Research Laboratory Department of Electrical and Computer Engineering McMaster University Hamilton Canada Department of Electronics Carleton University Ottawa Canada

This paper addresses physics-based design and yield optimization of MMICs. Multidimensional statistical models are considered for the physical, geometrical and process-related parameters of active and passive devices. An efficient gradient-based yield optimization technique is employed. The yield of an X-band amplifier is improved from 47.5% to 78.5%.

关键词： Design optimization MMICs Solid modeling Equivalent circuits Semiconductor process modeling Spirals FETs MIM capacitors Multidimensional systems Doping

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Gradient quadratic approximation scheme for yield-driven design

Gradient quadratic approximation scheme for yield-driven des...

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Microwave, MTT-S International Symposium

作者： J.W. Bandler R.M. Biernacki S.H. Chen J. Song S. Ye Q.J. Zhang Simulation Optimization Systems Research Laboratory and Department of Electrical and Computer Engineering McMaster University Hamilton Canada Department of Electronics Carleton University Ottawa Canada

A novel approach to the modeling of circuit response and gradients is proposed. The multidimensional quadratic approximation is exploited, and full advantage is taken of available gradient information. Efficiency and accuracy are demonstrated by gradient-based yield optimization of a filter and an MMIC (monolithic microwave integrate circuit) amplifier.< >

关键词： Circuit simulation Interpolation Computational modeling computer simulation Laboratories Multidimensional systems Information filtering Information filters MMICs Manufacturing

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Statistical modeling of GaAs MESFETs

Statistical modeling of GaAs MESFETs

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Microwave, MTT-S International Symposium

作者： J.W. Bandler R.M. Biernacki S.H. Chen J. Song S. Ye Q.J. Zhang Simulation Optimization Systems Research Laboratory and Department of Electrical and Computer Engineering McMaster University Hamilton ONT Canada Department of Electronics Carleton University Ottawa ONT Canada

The authors contrast the statistical extraction of GaAs MESFET equivalent circuit model parameters and physical model parameters from wafer measurements. It is observed that the equivalent-circuit model of A. Materka and T. Kacprzak (1985) provides a better match for individual devices but the model based on physical parameters of P.H. Ladbrooke (1989) provides a better estimate of device statistics. It is also shown that the Materka and Kacprzak equivalent-circuit model can accurately fit the data from which the model parameters are extracted, because it has fewer constraints than the physical model.< >

关键词： Gallium arsenide MESFETs Semiconductor device modeling Equivalent circuits Statistics FETs Data mining Voltage Electrons Computational modeling

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CAE Tools for Nonlinear systems Analysis and Design Based on Sinusoidal-Input Describing Functions

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IFAC Proceedings Volumes 1991年第4期24卷 89-94页

作者： J.R. O'Donnell J.H. Taylor Department of Electrical Computer and Systems Engineering Rensselaer Polytechnic Institute Troy NY 12180-3590 USA Control Systems Laboratory General Electric Corporate Research and Development P. O. Box 8 Schenectady NY 12301 USA

We report on recent progress in the development of a computer-aided engineering (CAE) environment for nonlinear control system analysis and design based on sinusoidal-input describing function (SIDF) methods. Several major additions have been made to our nonlinear controls CAE software: ACSL macros were developed to allow the generation of SIDF models of nonlinear plants in a manner analogous to that of the SIMNON-based software developed earlier, and MATLAB routines were developed for the analysis of these models and for the design of general nonlinear controllers based on them. This software provides an integrated tool set for treating very general nonlinear systems with no restrictions on system order, number of nonlinearities, configuration, or nonlinearity type. Based on the new software presented here, the use of SIDF-based nonlinear control system analysis and design methods is substantially easier to carry out and more powerful than before

关键词： Nonlinear control systems describing functions control system design computeraided design computer software

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Parasitic bipolar transistor induced latch and degradation in SOI MOSFET's

Parasitic bipolar transistor induced latch and degradation i...

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IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

作者： T.-D. Her P.S. Liu D.S. Quon G.P. Li R. Kjar J. White Advanced Semiconductor Device Research Laboratory Department of Electrical & Computer Engineering University of California Irvine CA USA Digital Communications Division Rockwell International Corporation Newport Beach CA USA

Direct measurement data show close correlation between the turn-on of a parasitic source-body-drain bipolar transistor and the single-transistor latch in SOI (silicon-on-insulator) MOSFETs. Interface state density generation and hot hole trapping in the gate oxide have been observed for SOI MOSFETs biased in this latch regime. Furthermore, experimental and simulation results show that SOI MOSFETs in the latch state are more immune to hot-carrier stresses than in the nonlatch state. The activation of a parasitic bipolar transistor is shown to induce the single-transistor latch and cause the degradation in SOI MOSFETs. However, the higher floating-body potential in SOI MOSFETs tends to make them less vulnerable to hot-carrier stress.< >

关键词： Bipolar transistors Degradation MOSFET circuits Hot carriers Stress Interface states Current measurement Laboratories Data engineering Digital communication

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A parallel algorithm for logic simulation on transputer networks

A parallel algorithm for logic simulation on transputer netw...

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Great Lakes Symposium on VLSI

作者： S. Srinivas A. Basu A. Paulraj L.M. Patnaik Department of Electrical and Computer Engineering Concordia University Montreal QUE Canada Centre for Development of Advanced Computing Bangalore India Microprocessor Applications Laboratory Supercomputing Education and Research Center Department of Computer Science and Automation Indian Institute of Science Bangalore India

The authors present a parallel algorithm for logic simulation of VLSI circuits. It is implemented on a network of transputers connected in a ring topology. The approach is based on partitioning a functionality matrix representation of the circuit among the transputers and adopting a data flow technique for the solution. A significant aspect of the algorithm is that it overlaps computation with communication, thereby reducing the communication overhead. It also attempts even distribution of load in order to reduce processor idle time. The algorithm possesses the advantages of ease of implementation and ease of extension to incorporate additional parameters for simulation. Performance results of the algorithm are given.< >

关键词： Parallel algorithms Circuit simulation Computational modeling Concurrent computing Application software Logic circuits Very large scale integration Algorithm design and analysis Logic design Design automation

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InGaAs/InP submicron gate microwave power transistors for 20 GHz applications

InGaAs/InP submicron gate microwave power transistors for 20...

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Indium Phosphide and Related Materials Conference

作者： G.A. Johnson M.D. Biedenbender V.J. Kapoor L.J. Messick R. Nguyen D. Schmitz H. Jurgensen Electronic Devices and Materials Research Laboratory Department of Electrical and Computer Engineering University of Cincinnati Cincinnati OH USA Naval Ocean Systems Center San Diego CA USA Aixtron Corporation Aachen Germany

Results of DC characteristic and RF power performance measurements on depletion mode InGaAs MISFETs with submicron gate lengths fabricated using an epitaxial process are presented. At 18 GHz, an output power density of 0.92 W/mm was obtained at an input power of 19.5 dBm. The corresponding gain and power-added efficiency were 3.2 dB and 29% respectively. The highest power-added efficiency obtained was 32% with a corresponding power gain and output power density of 4.3 dB and 0.86 W/mm, respectively, at an input power of 18 dBm. At 20 GHz, an output power density of 0.79 W/mm was obtained with a corresponding gain and power-added efficiency of 3.0 dB and 23%, respectively. The highest power-added efficiency was 25% at 0.73 W/mm output power density and 4.8 dB gain.< >

关键词： Indium gallium arsenide Indium phosphide Power transistors MISFETs Power generation Lattices Plasma temperature Gold Frequency Fabrication

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Neural networks for sidescan sonar automatic target detection

Neural networks for sidescan sonar automatic target detectio...

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IEEE Workshop on Neural Networks for Signal Processing

作者： M.J. LeBlanc E. Manolakos Fault-Tolerant Systems Division The Charles Stark Draper Laboratory Inc. Cambridge MA USA Communications and Digital Signal Processing Center of Research and Graduate Studies Electrical & Computer Engineering Department Northeastern University Boston MA USA

The goal of this research is to develop a multi-layer feedforward neural network architecture which can distinguish targets (in this case, mines) from background clutter in sidescan sonar images. The network is to be implemented on a hardware neurocomputer currently in development at CSDL, with the goal of eventual real-time performance in the field. A variety of neural network architectures are developed, simulated, and evaluated in an attempt to find the best approach for this particular application. It has been found that classical statistical feature extraction is outperformed by a much less computationally expensive approach that simultaneously compresses and filters the raw data by taking a simple mean.< >

关键词： Neural networks Sonar detection Object detection Multi-layer neural network Feedforward neural networks Neural network hardware computer architecture Computational modeling Feature extraction Filters

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