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Extended Abstracts of the 6th International Workshop on Junction Technology, IWJT '06

作者： Lee, Ho Rhee, Hwa Sung Ueno, Tetsuji Kim, Myung Sun Yi, Ji Hye Cho, Hans S. Chung, Youngsu Kim, Seulgi Baik, Hion Suck Feng, Lucia Wang, Yun Hautala, John Skinner, Wesley Bae, Geum-Jong Lee, Nae-In Kang, Ho-Kyu Advanced Process Development Project Team Semiconductor Business Samsung Electronics Co. Ltd. SAIT San #24 Nongseo-Ri Kiheung-Eup Kyunggi-Do 449-900 Korea Republic of Ultratech. 3050 Zanker Road San Jose Epion Corp. 37 Manning Road Billercia MA 01821 United States

ISBN: (纸本)1424400473

High energy borane (B2H6) gas cluster ion beam (GCIB) successfully enables a sub-10nm box-shaped dopant profile without channeling tail, and steep gradient (2.5nm/dec) in lateral direction. pFET using GCIB source/drain extension shows superior suppression of short channel effects and reduces the dependency of drive current on gate overlap capacitance variation for scaled devices. Moreover, the perimeter leakage component in p+/n-well junction was reduced compared to the conventional co-implantation process with pre-amorphization, which might come from novel self-amorphization mechanism by energized clusters without foreign impurities such as Ge and F. For further scaled devices, GCIB can provide more efficient boron activation by laser spike annealing (LSA) while maintaining the scaled extension profile by combination with the reduced temperature spike RTA. © 2006 IEEE.

关键词： Semiconductor junctions

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Reliability issues and models of sub-90nm NAND flash memory cells

Reliability issues and models of sub-90nm NAND flash memory ...

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ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology

作者： Yang, Hong Kim, Hyunjae Park, Sung-Il Kim, Jongseob Lee, Sung-Hoon Choi, Jung-Ki Hwang, Duhyun Kim, Chulsung Park, Mincheol Lee, Keun-Ho Park, Young-Kwan Shin, Jai Kwang Kong, Jeong-Taek Memory Division CAE Team Samsung Electronics Co. Ltd. San #16 Banwol-Dong Hwasung-City Gyeonggi-Do 445-701 Korea Republic of Nano CSE Project Team Samsung Advanced Institute of Technology Korea Republic of R and D TEST Engineering Group Samsung Electronics Co. Ltd. Korea Republic of Process Development Team Samsung Electronics Co. Ltd. Korea Republic of Flash Process Architecture Team Semiconductor Business Samsung Electronics Co. Ltd. Korea Republic of

ISBN: (纸本)1424401615

The reliability issues, including 100k cycle's endurance and 2 hours high temperature storage (HTS: 150°C, 200° and 250°C) of sub-90nm NAND Flash cells, are studied. Furthermore, the trap generation models in endurance and interface trap recovery model in HTS are proposed. Endurance characteristics show that the interface trap and bulk trap generation have a power-dependence on program/erase cycle count (ΔNit, ΔNot, ∝ cycle). The exponent of interface trap generation both program and erase are 0.62;while in bulk trap generation, the exponent for the cycle count is 0.30, which is extracted only from the erased cells due to varying stored charges of programmed cells during tunnel oxide degradation. The HTS characteristics show that the interface trap recovery and electron-detrapping are the major mechanisms for sub-90nm NAND Flash memory, while stress induced leakage current (SILC) is almost negligible. Thus, based on the reaction-diffusion (R-D) model and Arrhenius approximation, the simplified interface recovery model in HTS is proposed as: dNit/N it=-k0·exp(-Ea/kBT) ·dt. © 2006 IEEE.

关键词： Electric batteries

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Self-Amorphizing Gas Cluster Ion Beam Technology and Combination with Laser Spike Anneal for Highly Scaled Source Drain Junction

Self-Amorphizing Gas Cluster Ion Beam Technology and Combina...

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International Workshop on Junction Technology

作者： Ho Lee Hwa Sung Rhee T. Ueno Myung Sun Kim Ji Hye Yi H.S. Cho Youngsu Chung Seulgi Kim Hion Suck Baik L. Feng Yun Wang J. Hautala W. Skinner Geum-Jong Bae Nae-In Lee Ho-yu Kang Advanced Process Development Project Team Semiconductor Business Samsung Electronics Company Limited South Korea SAIT Yongin si Kyunggi South Korea Ultratech lnc. San Jose USA Epion Corporation Billerica MA USA

ISBN: (纸本)1424400473

High energy borane (B 2 H 6 ) gas cluster ion beam (GCIB) successfully enables a sub-10 nm box-shaped dopant profile without channeling tail, and steep gradient (2.5 nm/dec) in lateral direction. pFET using GCIB source/drain extension shows superior suppression of short channel effects and reduces the dependency of drive current on gate overlap capacitance variation for scaled devices. Moreover, the perimeter leakage component in p+/n-well junction was reduced compared to the conventional co-implantation process with pre-amorphization, which might come from novel self-amorphization mechanism by energized clusters without foreign impurities such as Ge and F. For further scaled devices, GCIB can provide more efficient boron activation by laser spike annealing (LSA) while maintaining the scaled extension profile by combination with the reduced temperature spike RTA

关键词： Ion beams Gas lasers Annealing Boron Temperature Implants Logic testing Sun Tail Capacitance

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Novel charge trap devices with NCBO trap layers for NVM or image sensor

Novel charge trap devices with NCBO trap layers for NVM or i...

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2006 International Electron Devices Meeting, IEDM

作者： Joo, Kyong-Hee Moon, Chang-Rok Lee, Sung-Nam Wang, Xiofeng Yang, Jun Kyu Yeo, In-Seok Lee, Duckhyung Nam, Okhyun Chung, U.-In Moon, Joo Tae Ryu, Byung-Il Process Development Team Memory Division Samsung Electronics Co. Ltd. San#24 Nongseo-Dong Giheung-Gu Yongin-City Gyeonggi-Do 446-711 Korea Republic of Technology Development Team Memory Division Samsung Electronics Co. Ltd. San#24 Nongseo-Dong Giheung-Gu Yongin-City Gyeonggi-Do 446-711 Korea Republic of Photonics Project Team Samsung Advanced Institute of Technology P.O.BOX. 111 Suwon 440-600 Korea Republic of

ISBN: (纸本)1424404398

ZnO or AlxGa1-xN charge trap device showed large memory window (>7V) with fast P/E speed (±17 V, 100 μs) and excellent retention (10-year memory window of 6 V with small charge loss rate;∼1/5 of that of Si3N4). GaN and ZnO trap devices also showed the photo-sensitive programming due to their optoelectronics properties, providing the possibility of developing new type of high performance image sensor (QE ∼ 80%).

关键词： Zinc oxide

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Novel Charge Trap Devices with NCBO Trap Layers for NVM or Image Sensor

Novel Charge Trap Devices with NCBO Trap Layers for NVM or I...

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International Electron Devices Meeting (IEDM)

作者： Kyong-Hee Joo Chang-Rok Moon Sung-Nam Lee Xiofeng Wang Jun Kyu Yang In-Seok Yeo Duckhyung Lee Okhyun Nam U-In Chung Joo Tae Moon Byung-I Ryu Process Development Team Memory Division Semiconductor Business Samsung Electronics Company Limited South Korea Technology Development Team Memory Division Semiconductor Business Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Photonics Project Team Samsung Advanced Institute of Technology Suwon South Korea

ZnO or Al x Ga 1-x N charge trap device showed large memory window (>7V) with fast P/E speed (plusmn17 V, 100 (_is) and excellent retention (10-year memory window of 6 V with small charge loss rate; ~l/5 of that of Si 3 N 4 ). GaN and ZnO trap devices also showed the photo-sensitive programming due to their optoelectronics properties, providing the possibility of developing new type of high performance image sensor (QE ~ 80%)

关键词： Image sensors Zinc oxide Electron traps Conducting materials Gallium nitride Tunneling Substrates Nanocrystals Nonvolatile memory Moon

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Linewidth dependence of grain structure and stress in damascene Cu lines

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Journal of Applied Physics 2006年第2期99卷 1-6页

作者： Paik, Jong-Min Park, Il-Mok Joo, Young-Chang Park, Ki-Chul School of Materials Science and Engineering Seoul National University Seoul 151-744 Korea Republic of Advanced Process Development Project Team System LSI Division Samsung Electronics Co. Ltd. San #24 Nongseo-Ri Young-In City Gyeonggi-Do 449-711 Korea Republic of

Damascene Cu interconnects show significant differences in both their microstructural and stress behavior as compared to those of Al interconnects patterned using the etching process. Thermal stresses build up during the successive thermal cycles due to the differences in the coefficients of thermal expansion of the component materials. Other than these thermal stresses, growth stresses originating from grain growth develop in damascene Cu interconnects as well. In this study, the linewidth dependence of the stress in damascene Cu was examined experimentally, as well as by numerical simulation. The stresses of damascene Cu with widths ranging from 0.13 to 2 μm were measured using x-ray diffraction, and the measured hydrostatic stress was found to increase with increasing linewidth, in contrast to the typical behavior of Al interconnects. Microstructure analysis using transmission electron microscopy revealed that the grain sizes increased with increasing line dimensions. The increase in stress in the interconnect with increasing dimensions is attributed to the larger grain size, which induces higher growth stress in addition to the thermal stress. The contribution of the growth and thermal stresses of the damascene lines were quantified based on the grain size data utilizing finite element analysis. In this way, the linewidth dependence of the hydrostatic stress of damascene Cu was clearly explained. Finally, the effect of growth stress on the stress-related reliability is discussed. © 2006 American Institute of Physics.

关键词： Copper

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Pre-Metal Dielectric Stress Engineering by a Novel Plasma Treatment and Integration Scheme for nMOS Performance Improvement

Pre-Metal Dielectric Stress Engineering by a Novel Plasma Tr...

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Symposium on VLSI Technology

作者： Y.-K. Jeong D.S. Shin A. Kim I. Yoon S.-W. Nam S.-J. Lee K.-K. Park K. Kim H.-J. Shin K. Roh K.-H. Kang Y.-H. Choi G.-H. Seo K. Lee K. Chu N.-I. Lee K.C. Kim Advanced Process Development Team Samsung Electronics Company Limited Yongin si Kyunggi South Korea Advanced Process Development Team Yongin-City Kyungki-Do Korea Adv. Process Dev. Team Samsung Electron. Co. Ltd. Kyungki-Do Technology Group 3 Samsung Electronics Company Limited Yongin si Kyunggi South Korea Technology Group 3 Yongin-City Kyungki-Do Korea Device Project Samsung Electronics Co. Ltd. Yongin-City Kyungki-Do Korea

For the first time, a transistor performance improvement is achieved by increasing the tensile stress of O 3 -TEOS pre-metal dielectric (PMD) using a novel plasma treatment and integration scheme. Plasma-treated O 3 -TEOS films show more tensile stress value about twice than that of an as-deposited O 3 -TEOS film. The novel process shows up to 10% improvement of I on for nMOS without any cost of pMOS degradation

关键词： Dielectrics MOS devices Tensile stress Plasma applications Plasma measurements Performance gain Compressive stress Plasma simulation Stress measurement Thickness measurement

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Pre-metal dielectric stress engineering by a novel plasma treatment and integration scheme for nMOS performance improvement

Pre-metal dielectric stress engineering by a novel plasma tr...

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2006 Symposium on VLSI Technology, VLSIT

作者： Jeong, Yong-Kuk Shin, Dong Suk Kim, Andrew Yoon, Il Young Nam, Seo-Woo Lee, Seung-Jin Park, Ki-Kwan Kim, K.C. Shin, Hong-Jae Roh, Ki Bong Kang, Ki-Ho Choi, Yong-Ho Seo, Gi-Ho Lee, Kwon Chu, Kang Soo Lee, Nae-In Advanced Process Development Team San#24 Nongseo-Dong Giheung-Gu Yongin-City Kyungki-Do 449-900 Korea Republic of Technology Group 3 San#24 Nongseo-Dong Giheung-Gu Yongin-City Kyungki-Do 449-900 Korea Republic of Device Project Samsung Electronics Co. Ltd. San#24 Nongseo-Dong Giheung-Gu Yongin-City Kyungki-Do 449-900 Korea Republic of

ISBN: (纸本)1424400058

For the first time, a transistor performance improvement is achieved by increasing the tensile stress of O3-TEOS pre-metal dielectric (PMD) using a novel plasma treatment and integration scheme. Plasma-treated O 3-TEOS films show more tensile stress value about twice than that of an as-deposited O3-TEOS film. The novel process shows up to 10% improvement of Ion for nMOS without any cost of pMOS degradation. © 2006 IEEE.

关键词： Dielectric materials

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Reliability Issues and Models of sub-90nm NAND Flash Memory Cells

Reliability Issues and Models of sub-90nm NAND Flash Memory ...

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2006 8th International Conference on Solid-State and Integrated Circuit Technology

作者： Hong Yang Hyunjae Kim Sung-il Park Jongseob Kim Sung-Hoon Lee Jung-Ki Choi Duhyun Hwang Chulsung Kim Mincheol Park Keun-Ho Lee Young-Kwan Park Jai Kwang Shin Jeong-Taek Kong CAE Team Memory DivisionSemiconductor BusinessSamsung Electronics Co.Ltd.San Nano CSE Project Team Samsung Advanced Institute of Technology R&D TEST Engineering Group Samsung Electronics Co.Ltd. Process Development Team Samsung Electronics Co.Ltd. Flash Process Architecture Team Semiconductor BusinessSamsung Electronics Co.Ltd.

ISBN: (纸本)1424401607

The reliability issues,including 100k cycle's endurance and 2 hours high temperature storage（HTS:150℃, 200℃and 250℃） of sub-90nm NAND Flash cells,are ***,the trap generation models in endurance and interface trap recovery model in HTS are *** characteristics show that the interface trap and bulk trap generation have a power-dependence on program/erase cycle count(△N,△N∝cycle^m).The exponent of interface trap generation both program and erase are 0.62;while in bulk trap generation,the exponent for the cycle count is 0.30,which is extracted only from the erased cells due to varying stored charges of programmed cells during tunnel oxide *** HTS characteristics show that the interface trap recovery and electron-detrapping are the major mechanisms for sub-90nm NAND Flash memory,while stress induced leakage current（SILC） is almost ***,based on the reaction-diffusion （R-D）model and Arrhenius approximation,the simplified interface recovery model in HTS is proposed as:dN/N=-k·exp（-E/kT）.dt.

关键词： HTS Reliability Issues and Models of sub-90nm NAND Flash Memory Cells

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PBTI & HCI characteristics for High-k Gate dielectrics with Poly-Si & MIPS (Metal Inserted Poly-Si Stack) gates

PBTI & HCI characteristics for High-k Gate dielectrics with ...

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2005 IEEE International Reliability Physics Symposium Proceedings, 43rd Annual

作者： Jung, Hyung-Suk Han, Sung Kee Kim, Min Joo Kim, Jong Pyo Kim, Yun-Seok Lim, Ha Jin Doh, Seek Joo Lee, Jung Hyoung Yu, Mi Young Lee, Jong-Ho Lee, Nae-In Kang, Ho-Kyu Park, Seong Geon Kang, Sang Bom Advanced Process Development Project System LSI Business Samsung Electronics Co. Ltd. San #24 Nongseo-Ri Kiheung-Eup Yongin-City Kyunggi-Do 449-711 Korea Republic of Process Development Team 2 Semiconductor RandD Center Samsung Electronics Co. Ltd.

ISBN: (纸本)0780388038

Reliability characteristics of high-k gate dielectrics with poly-Si gate and metal inserted poly-Si stack (MIPS) gate are investigated in terms of positive bias temperature instability (PBTI) and hot carrier injection (HCI) characteristics. The results indicate that the dopants (P or As) from the poly-Si severely degrade PBTI and HCI characteristics. Therefore, the high-k/MIPS structure, which is not influenced by gate dopants, shows significant improvement in PBTI and HCI characteristics. For the same reason, the worst HCI condition of high-k/poly-Si structure is Vg=V d instead of Vg at Isub_max, while that of high-k/MIPS structure is Vg at Isub_max. © 2005 IEEE.

关键词： Dielectric materials

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