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Ultimate solution for low thermal budget gate spacer and etch stopper to retard short channel effect in sub-90 nm devices

Ultimate solution for low thermal budget gate spacer and etc...

引用

Symposium on VLSI Technology

作者： Jong-Ho Yang Jae-Eun Park Joo-Won Lee Kang-Soo Chu Ja-Hum Ku Moon-Han Park Nae-In Lee Hee-Sung Kang Myung-Hwan Oh Jun-Ha Lee Ho-Kyu Kang Kwang-Pyuk Suh Advanced Process Development Project Samsung Electronics Co. Ltd. Yonzin-City Kyungai-Do Korea System LSI Division Samsung Electronics Co. Ltd. South Korea System LSI Division Samsung Electronics Co. Ltd. Memory Division Samsung Electronics Co. Ltd.

ISBN: (纸本)489114033X

For the first time, by employing low thermal budget processes of ALD SiO/sub 2/ and ALD SiN as gate spacer and silicide blocking layer, the short channel effects of CMOSFETs are significantly suppressed. Using the ALD SiO/sub 2/ and ALD SiN processes, we achieved excellent roll-off characteristics of threshold voltage in PMOS, which results in 10% increase of drive current and 15% decrease of inverter delay time. Furthermore, gate oxide reliability and static noise margin of 6T-SRAM bit cell with ALD SiC/sub 2/SiN processes are comparable to those with conventional high temperature CVD SiO/sub 2//SiN processes. In conclusion, ALD SiO/sub 2/ and ALD SiN processes of extremely low thermal budget are successfully implemented to sub-90 nm CMOSFETs.

关键词： Etching Silicon compounds CMOSFETs Plasma temperature Large scale integration Silicides Threshold voltage Inverters Delay effects Thermal degradation

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A new double-layered structure for mass-production-worthy CMOSFETs with poly-SiGe gate

A new double-layered structure for mass-production-worthy CM...

引用

2002 Symposium on VLSI Technology Digest of Technical Papers

作者： Rhee, Hwa Sung Lee, Jung Il Kim, Sang Su Bae, Geum Jong Lee, Nae-In Kim, Do Hyung Hong, Jung In Kang, Ho-Kyu Suh, Kwang Pyuk Advanced Process Development Project System LSI Business San #24 Nongseo-Ri Kiheung-Eup Yongin-Si Kyunaggi-Do 449-900 Korea Republic of

A new double-layered structure of poly-Si/SiGe gate has been proposed to improve the current performance of CMOSFETs and the reproducibility of devices. The double-layered poly-Si/SiGe stack has small-sized (columnar) grains in the lower poly-SiGe layer and large-sized grains in the upper poly-Si layer. The new structure can suppress Ge diffusion into the upper poly-Si layer during CMOS process, resulting in enhanced current performance and better sheet resistance distribution to meet gate height scaling requirements sub-0.1μm CMOSFETs. Mass productive 8M SRAM with both the smallest cell size and the enhanced operation speed by 20% was successfully fabricated using the proposed poly-SiGe gate structure.

关键词： MOSFET devices

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Implanted-ion dose variation from Si surface status of sub-nm scale on 90 nm ULSI process 14

Implanted-ion dose variation from Si surface status of sub-n...

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2002 14th IEEE International Conference on Ion Implantation Technology, IIT 2002

作者： Kase, Masataka Kubo, Tomohiro Watanabe, Kiyoshi Okabe, Ken-Ichi Nakao, Hiroshi Advanced LSI Development Division Fujitsu Limited Akiruno Tokyo Japan Fujitsu VLSI Process Technology Laboratory Limited Akiruno Tokyo Japan C Project Fujitsu Laboratories Limited Akiruno Tokyo Japan

ISBN: (纸本)0780371550

To make a shallow junction, understanding the influence of the Si surface status is quite important to achieve stable-dose implanted layers. The causes or dose variation can be a sub-nm screening/capping oxide and silicon loss, which originate from the wet chemical processes, the photo resist processes and the clean room environment. These phenomena are examined using SIMS, sheet resistance and the transistor characteristics of a 90 nm node of high end CMOS logic device. © 2002 IEEE.

关键词： Logic devices

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Practical next generation solution for stand-alone and embedded DRAM capacitor

Practical next generation solution for stand-alone and embed...

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2002 Symposium on VLSI Technology Digest of Technical Papers

作者： Lee, Jong-Ho Lee, Jung-Hyoung Kim, Yun-Seok Jung, Hyung-Seok Lee, Nae-In Kang, Ho-Kyu Suh, Kwang-Pyuk Advanced Process Development Project System LSI Business Samsung Electronics Co. Ltd. San #24 Nongseo-Ri Kiheung-Eup Yongin-City Kyunggi-Do 449-711 Korea Republic of

For the first time, MIS capacitor with HfO2-Al2O3 laminate is successfully demonstrated. The effective oxide thickness (EOT) of 21 Å with acceptable low leakage current has been achieved at cylinder-type MIS capacitor. The EOT of 21 Å is the smallest value reported for MIS capacitor with TiN electrode regardless of dielectric material. We have confirmed the feasibility of reducing EOT in spite of simple process without pre-deposition treatment. HfO2-Al2O3 laminate is also useful for SIS capacitor and can satisfy the needs of MIM capacitor for the next generation without changing electrode material. Therefore, this technology is not far away from present but a practical approach adequate for chip-making industry.

关键词： Capacitors

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Poly-Si gate CMOSFETs with HFO2-AL2O3 laminate gate dielectric for low power applications

Poly-Si gate CMOSFETs with HFO2-AL2O3 laminate gate dielectr...

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2002 Symposium on VLSI Technology Digest of Technical Papers

作者： Lee, Jong-Ho Kim, Yun-Seok Jung, Hyung-Seok Lee, Jung-Hyoung Lee, Nae-In Kang, Ho-Kyu Ku, Ja-Hum Kang, Hee Sung Kim, Youn-Keun Cho, Kyung-Hwan Suh, Kwang-Pyuk Advanced Process Development Project System LSI Business Samsung Electronics Co. Ltd. San #24 Nongseo-Ri Kiheung-Eup Yongin-City Kyunggi-Do 449-711 Korea Republic of

For the first time, we have integrated poly-Si gate CMOS-FETs with HfO2-Al2O3 laminate gate dielectric (EOT=14.6Å) grown by Atomic Layer Deposition (ALD). The gate leakage currents are 3.7μA/cm2 (Vg=+1.0V) for nMOSFET and 0.2 μA/cm2 (Vg=-1.0V) for pMOSFET. These extremely low leakage currents sufficiently satisfy the specification (EOT= 12-20Å, Jg=2.2mA/cm2) estimated by ITRS. The fixed charge is decreased using HfO2-Al2O3 laminate gate dielectric, and consequently flatband voltage (Vfb) shift is within 0.20V compared with the Vfb of nitrided SiO2 control. In addition, the low gate induced drain leakage (GIDL) is obtained using HfO2-Al2O3 laminate gate dielectric. Ion vs. Ioff plots of the planar CMOS transistor with high-k is shown for the first time in this paper. The measured saturation currents at 1.2V Vdd are 430μA/μm (IΩΠ=10nA/μm) for nMOSFET and 160μA/μm (IΩΠ=10nA/μm) for pMOSFET. These are the highest currents compared with previous reports for the planar poly-Si gate CMOSFETs with high-k gate dielectric.

关键词： MOSFET devices

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Practical next generation solution for stand-alone and embedded DRAM capacitor

Practical next generation solution for stand-alone and embed...

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Symposium on VLSI Technology

作者： Jong-Ho Lee Jung-Hyoung Lee Yun-Seok Kim Hyung-Seok Jung Nae-In Lee Ho-Kyu Kang Kwang-Pyuk Suh Advanced Process Development Project Samsung Electronics Company Limited Yongin si Kyunggi South Korea Advanced Process Development Project System LSI Business Samsung Electronics Company Limited Yongin si Kyunggi South Korea

ISBN: (纸本)078037312X

For the first time, MIS capacitors with HfO/sub 2/-Al/sub 2/O/sub 3/ laminate are successfully demonstrated. The effective oxide thickness (EOT) of 21 /spl Aring/ with an acceptably low leakage current has been achieved for a cylinder-type MIS capacitor. The EOT of 21 /spl Aring/ is the smallest value reported for MIS capacitors with TiN electrodes regardless of dielectric material. We have confirmed the feasibility of reducing EOT in spite of the simple process without a pre-deposition treatment. HfO/sub 2/-Al/sub 2/O/sub 3/ laminate is also useful for SIS capacitors and can satisfy the needs of MIM capacitors for the next generation without changing electrode material.

关键词： Random access memory Laminates MIM capacitors Leakage current Hafnium oxide High-K gate dielectrics Electrodes Dielectric materials High K dielectric materials Dielectric constant

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Poly-Si gate CMOSFETs with HfO/sub 2/-Al/sub 2/O/sub 3/ laminate gate dielectric for low power applications

Poly-Si gate CMOSFETs with HfO/sub 2/-Al/sub 2/O/sub 3/ lami...

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Symposium on VLSI Technology

作者： Jong-Ho Lee Yun-Seok Kim Hyung-Seok Jung Jung-Hyoung Lee Nae-In Lee Ho-Kyu Kang Ja-Hum Ku Hee Sung Kang Youn-Keun Kim Kyung-Hwan Cho Kwang-Pyuk Suh Advanced Process Development Project System LSI Business Samsung Electronics Company Limited Yongin si Kyunggi South Korea

ISBN: (纸本)078037312X

For the first time, we have integrated poly-Si gate CMOS-FETs with HfO/sub 2/-Al/sub 2/O/sub 3/ laminate gate dielectric (EOT=14.6 /spl Aring/) grown by Atomic Layer Deposition (ALD). The gate leakage currents are 3.7 /spl mu/A/cm/sup 2/ (Vg=+1.0 V) for nMOSFET and 0.2 /spl mu/A/cm/sup 2/ (Vg=-1.0 V) for pMOSFET. These extremely low leakage currents sufficiently satisfy the specification (EOT= 12/spl sim/20 /spl Aring/, Jg=2.2 mA/cm/sup 2/) estimated by ITRS. The fixed charge is decreased using HfO/sub 2/-Al/sub 2/O/sub 3/ laminate gate dielectric, and consequently flatband voltage (Vfb) shift is within 0.20 V compared with the Vfb of nitrided SiO/sub 2/ control. In addition, a low gate induced drain leakage (GIDL) is obtained using HfO/sub 2/-Al/sub 2/O/sub 3/ laminate gate dielectric. I/sub on/ vs. I/sub off/ plots of the planar CMOS transistor with high-k is shown for the first time in this paper. The measured saturation currents at 1.2 V Vdd are 430 /spl mu/A//spl mu/m (I/sub off/=10 nA//spl mu/m) for nMOSFET and 160 /spl mu/A//spl mu/m (I/sub off/=10 nA//spl mu/m) for pMOSFET. These are the highest currents compared with previous reports for the planar poly-Si gate CMOSFETs with high-k gate dielectric.

关键词： CMOSFETs Hafnium oxide MOSFET circuits Laminates Leakage current Channel bank filters Atomic layer deposition Voltage control High K dielectric materials High-K gate dielectrics

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A new double-layered structure for mass-production-worthy CMOSFETs with poly-SiGe gate

A new double-layered structure for mass-production-worthy CM...

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Symposium on VLSI Technology

作者： Hwa Sung Rhee Jung Il Lee Sang Su Kim Geum Jong Bae Nae-In Lee Do Hyung Kim Jung In Hong Ho-Kyu Kang Kwang Pyuk Suh Advanced Process Development Project System LSI Business Yongin si Kyunggi South Korea Samsung Electronics Company Limited Yongin si Kyunggi South Korea

ISBN: (纸本)078037312X

A new double-layered structure of poly-Si/SiGe gate has been proposed to improve the current performance of CMOSFETs and the reproducibility of devices. The double-layered poly-Si/SiGe stack has small-sized (columnar) grains in the lower poly-SiGe layer and large-sized grains in the upper poly-Si layer. The new structure can suppress Ge diffusion into the upper poly-Si layer during CMOS process, resulting in enhanced current performance and better sheet resistance distribution to meet gate height scaling requirements of sub-0.1 /spl mu/m CMOSFETs. A mass productive 8 Mbit SRAM with both the smallest cell size and enhanced operation speed by 20% was successfully fabricated using the proposed poly-SiGe gate structure.

关键词： CMOSFETs Silicon germanium Germanium silicon alloys CMOS process Reproducibility of results Grain boundaries Random access memory Fluctuations Large scale integration Boron

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Mass-productive ultra-low temperature ALD SiO2 process promising for sub-90 nm memory and logic devices

Mass-productive ultra-low temperature ALD SiO2 process promi...

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2002 IEEE International Devices Meeting (IEDM)

作者： Park, Jae-Eun Ku, Ja-Hum Lee, Joo-Won Yang, Jong-Ho Chu, Kang-Soo Lee, Seung-Hwan Park, Moon-Han Lee, Nae-In Kang, Ho-Kyu Suh, Kwang-Pyuk Cho, Byoung-Ha Kim, Byoung-Chul Shin, Cheol-Ho Advanced Process Development Project System LSI Division Samsung Electronics Co. Ltd. San #24 Nongseo-Ri Kiheung-Eup Yongin-City Kyunggi-Do 449-711 Korea Republic of Moohan Inc. #5-1 Chaam-Dong Chonan-City Chungchongnam-Do 330-200 Korea Republic of

For the first time, ultra-low temperature ALD SiO2 is successfully developed and applied on W/WN/poly-Si stack gate as a dual spacer for the enhancement of data retention time. ALD SiO2 deposition is performed at 75 °C using HCD and H2O as precursors and pyridine as a catalyst. Using ALD SiO2 process, SiO2 layer is deposited on W/WN/poly-Si stack gate without W oxidation. The gate resistances of W/WN/poly-Si stack gate do not exhibit any difference between SiN single spacer and SiO2/SiN dual spacer schemes, which indicates that W oxidation does not occur during the ALD SiO2 deposition for the formation of dual spacer. Conclusively, the significant improvement(>50%) of data retention time is achieved by employing SiO2/SiN dual spacer at W/WN/poly-Si stack gate in 130nm DRAM device. In addition, excellent short channel characteristics of Vth is identified by applying low temperature ALD SiO2 layer as a dual spacer on sub-100 nm SRAM device.

关键词： Semiconductor storage

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Mass-productive ultra-low temperature ALD SiO/sub 2/ process promising for sub-90 nm memory and logic devices

Mass-productive ultra-low temperature ALD SiO/sub 2/ process...

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International Electron Devices Meeting (IEDM)

作者： Jae-Eun Park Ja-Hum Ku Joo-Won Lee Jong-ho Yang Kang-Soo Chu Seung-Hwan Lee Moon-Han Park Nae-In Lee Ho-Kyu Kang Kwang-Pyuk Suh Byoung-Ha Cho Byoung-Chul Kim Cheol-Ho Shin Advanced Process Development Project System LSI Division Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Moohan Inc. Chonan Chungcheongnam South Korea

ISBN: (纸本)0780374622

For the first time, ultra-low temperature ALD SiO/sub 2/ is successfully developed and applied on W/WN/poly-Si stack gates as a dual spacer for the enhancement of data retention time. ALD SiO/sub 2/ deposition is performed at 75/spl deg/C using HCD and H/sub 2/O as precursors and pyridine as a catalyst. Using the ALD SiO/sub 2/ process, SiO/sub 2/ layers are deposited on W/WN/poly-Si stack gates without W oxidation. The gate resistances of the W/WN/poly-Si stack gates do not exhibit any difference between SiN single spacer and SiO/sub 2//SiN dual spacer schemes, which indicates that W oxidation does not occur during the ALD SiO/sub 2/ deposition for dual spacer formation. Conclusively, the significant improvement (>50%) of data retention time is achieved by employing SiO/sub 2//SiN dual spacers at W/WN/poly-Si stack gates in a 130 nm DRAM device. In addition, excellent short channel characteristics of Vth are identified by applying a low temperature ALD SiO/sub 2/ layer as a dual spacer on sub-100 nm SRAM devices.

关键词： Temperature Logic devices Oxidation Random access memory Silicon compounds Atomic layer deposition Annealing Rough surfaces Surface roughness Atomic measurements

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