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2006 International Interconnect Technology Conference, IITC

作者： Sakata, A. Yamashita, S. Omoto, S. Hatano, M. Wada, J. Higashi, K. Yamaguchi, H. Yosho, T. Imamizu, K. Yamada, M. Masunuma, M. Takahashi, S. Yamada, A. Hasegawa, T. Kaneko, H. Process and Manufacturing Engineering Center Semiconductor Company Toshibu Corporation Advanced CMOS Technology Department SoC R and D Center Semiconductor Company System LSI Division I Semiconductor Company Toshiba Corporation Semiconductor Technology Development Group Semiconductor Business Unit Sony Corporation 8 Shinsugita-cho Isogo-ku Yokohama Kanagawa 235-8522 Japan

ISBN: (纸本)1424401038

This paper elucidated for the first time that Titanium (Ti) is an excellent barrier metal(BM) material from the stand point of cost and perfonnance, especially for the porous low-k ILD materials. Both stress induced voiding (SIV) suppression and one order longer electromigration (EM) lifetime were obtained by introducing Ti instead of the conventional Tantalum (Ta). It has been considered that the smaller volume change when oxidized, and the existence of metallic Ti-O solid-solution phase for Ti would be the reason for its control of moisture penetration from the low-k ILD materials which resulted in excellent SIV suppression. No electrical resistance increase due to intermetallic reaction between Cu and Ti was observed. Furthermore, the suppression of Cu grain boundary migration was attributed to the segregation of Ti atoms at the Cu grain boundaries. This resulted in higher interconnect reliability. © 2006 IEEE.

关键词： Titanium

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Linewidth dependence of grain structure and stress in damascene Cu lines

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Journal of Applied Physics 2006年第2期99卷 1-6页

作者： Paik, Jong-Min Park, Il-Mok Joo, Young-Chang Park, Ki-Chul School of Materials Science and Engineering Seoul National University Seoul 151-744 Korea Republic of Advanced Process Development Project Team System LSI Division Samsung Electronics Co. Ltd. San #24 Nongseo-Ri Young-In City Gyeonggi-Do 449-711 Korea Republic of

Damascene Cu interconnects show significant differences in both their microstructural and stress behavior as compared to those of Al interconnects patterned using the etching process. Thermal stresses build up during the successive thermal cycles due to the differences in the coefficients of thermal expansion of the component materials. Other than these thermal stresses, growth stresses originating from grain growth develop in damascene Cu interconnects as well. In this study, the linewidth dependence of the stress in damascene Cu was examined experimentally, as well as by numerical simulation. The stresses of damascene Cu with widths ranging from 0.13 to 2 μm were measured using x-ray diffraction, and the measured hydrostatic stress was found to increase with increasing linewidth, in contrast to the typical behavior of Al interconnects. Microstructure analysis using transmission electron microscopy revealed that the grain sizes increased with increasing line dimensions. The increase in stress in the interconnect with increasing dimensions is attributed to the larger grain size, which induces higher growth stress in addition to the thermal stress. The contribution of the growth and thermal stresses of the damascene lines were quantified based on the grain size data utilizing finite element analysis. In this way, the linewidth dependence of the hydrostatic stress of damascene Cu was clearly explained. Finally, the effect of growth stress on the stress-related reliability is discussed. © 2006 American Institute of Physics.

关键词： Copper

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A study of water absorption induced-dielectric constant increase and its suppression on copper damascene interconnect structure with porous low-k (k=2.3) dielectrics

A study of water absorption induced-dielectric constant incr...

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9th International Interconnect Technology Conference (IITC)

作者： Nakamura, N. Matsunaga, N. Higashi, K. Shimada, M. Miyajima, H. Yamada, M. Enomoto, Y. Hasegawa, T. Shibata, H. Advanced CMOS Technology Department SoC R and D Center Toshiba Corporation Isogo-ku Yokohama Kanagawa 235-8522 8 Shinsugita-cho Japan Process and Manufacturing Engineering Center Semiconductor Company Toshiba Corporation Isogo-ku Yokohama Kanagawa 235-8522 8 Shinsugita-cho Japan System LSI Division I Semiconductor Company Toshiba Corporation Isogo-ku Yokohama Kanagawa 235-8522 8 Shinsugita-cho Japan Semiconductor Technology Development Group Semiconductor Business Unit Sony Corporation Isogo-ku Yokohama Kanagawa 235-8522 8 Shinsugita-cho Japan

ISBN: (纸本)1424401038

A key technology for realizing an effective k-value (keff) required for 45nm node is proposed. We studied the behavior of effective dielectric constant derived from capacitance of double-level copper interconnect wires with porous low-k materials in detail. The porous low-k materials easily absorb moisture due to process damage and the dielectric constant drastically increases. We have confirmed that if moisture-controlled robust process integration is performed, a reasonably effective dielectric constant (2.8) is obtained corresponding to the ideal bulk k-value (2.4). However, when the sealing of passivation films is broken, the effective dielectric constant increases to the level derived from that of the damaged blanket film. In order to ensure a target capacitance of copper interconnect wire with porous low-k material, it is indispensable to perfectly seal a whole device area from moisture uptake.

关键词： Capacitance

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Breakdown and conduction mechanisms of ALD HfSiON dielectric with TaN gate using carrier separation analysis

Breakdown and conduction mechanisms of ALD HfSiON dielectric...

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2005 IEEE International Reliability Physics Symposium Proceedings, 43rd Annual

作者： Doh, Seok Joo Lee, Jung Hyoung Kim, Jong Pyo Lee, Jong-Ho Kim, Yun-Seok Lim, Ha-Jin Jung, Hyung-Suk Han, Sung Kee Kim, Min Joo Lee, Nae-In Kang, Ho-Kyu Park, Seong Geon Kang, Sang Bom Advanced Process Development Project System LSI Business Samsung Electronics Co. Ltd. San #24 Nongseo-Ri Kiheung-Eup Yongin-City Kyunggi-Do 449-711 Korea Republic of Process Development Team 2 Semiconductor R and D Center Samsung Electronics Co. Ltd.

ISBN: (纸本)0780388038

For the first time, we evaluated breakdown and conduction mechanisms of ALD HfSiON with TaN gate. In the unstressed HfSiON, hole current dominates the gate leakage current. Under the SILC condition, the electron trap generation from the band edge of TaN gate and conduction band edge of Si substrate is accelerated, resulting in the increase of electron current. After soft breakdown of the dielectric, the electron current is predominant in the gate leakage. We demonstrate that the electron tunneling current mainly contributes to the degradation and breakdown of HfSiON dielectric with TaN gate. The conduction mechanism of the electron and hole is the Fowler-Nordheim tunneling. © 2005 IEEE.

关键词： Dielectric materials

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PBTI & HCI characteristics for High-k Gate dielectrics with Poly-Si & MIPS (Metal Inserted Poly-Si Stack) gates

PBTI & HCI characteristics for High-k Gate dielectrics with ...

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2005 IEEE International Reliability Physics Symposium Proceedings, 43rd Annual

作者： Jung, Hyung-Suk Han, Sung Kee Kim, Min Joo Kim, Jong Pyo Kim, Yun-Seok Lim, Ha Jin Doh, Seek Joo Lee, Jung Hyoung Yu, Mi Young Lee, Jong-Ho Lee, Nae-In Kang, Ho-Kyu Park, Seong Geon Kang, Sang Bom Advanced Process Development Project System LSI Business Samsung Electronics Co. Ltd. San #24 Nongseo-Ri Kiheung-Eup Yongin-City Kyunggi-Do 449-711 Korea Republic of Process Development Team 2 Semiconductor RandD Center Samsung Electronics Co. Ltd.

ISBN: (纸本)0780388038

Reliability characteristics of high-k gate dielectrics with poly-Si gate and metal inserted poly-Si stack (MIPS) gate are investigated in terms of positive bias temperature instability (PBTI) and hot carrier injection (HCI) characteristics. The results indicate that the dopants (P or As) from the poly-Si severely degrade PBTI and HCI characteristics. Therefore, the high-k/MIPS structure, which is not influenced by gate dopants, shows significant improvement in PBTI and HCI characteristics. For the same reason, the worst HCI condition of high-k/poly-Si structure is Vg=V d instead of Vg at Isub_max, while that of high-k/MIPS structure is Vg at Isub_max. © 2005 IEEE.

关键词： Dielectric materials

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New insight into stress induced voiding mechanism in Cu interconnects

New insight into stress induced voiding mechanism in Cu inte...

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IEEE 2005 International Interconnect Technology Conference, IITC

作者： Lee, Sun-Jung Lee, Soo-Geun Suh, Bong-Suk Shin, Hongjae Lee, Nae-In Kang, Ho-Kyu Suh, Gwangpyuk Advanced Process Development Team System LSI Business Samsung Electronics Co. Ltd. San#24 Nongseo-Ri Youngin-City Kyunggi-Do 449-711 Korea Republic of

ISBN: (纸本)078038752X

An effective method was used for the failure analysis of stress induced voids. Instead of conventional vertical inspection, lower wide copper surface connected to the via was investigated after removing the passivation layer and upper copper layer. Many voids were observed at the grain boundary area, regardless of via location. According to the step by step inspection of that surface, many small voids were generated at the grain boundary area after dielectric barrier deposition even before HTS(High temperature storage) test, and some of the voids were grown after HTS, preferentially at the grain boundary corners. This result implies that unlucky landing of via over the grain boundary area would be the main cause of stress induced void under the via. © 2005 IEEE.

关键词： Copper

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Data retention behavior in the Embedded SONOS Nonvolatile Memory Cell

Data retention behavior in the Embedded SONOS Nonvolatile Me...

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63rd Device Research Conference, DRC'05

作者： Chae, H.S. Jung, Y.S. Seo, S. Han, J.H. Hyun, J.W. Park, G.W. Um, M.Y. Kim, J.-H. Lee, B.J. Kim, K.C. Cho, I.W. Bae, G.J. Lee, N.I. Kang, S.T. Kim, C.W. Devices Lab Samsung Advanced Institute of Technology San 14 Nongseo-ri Kihung-up Yongin-si Kyungki-do Korea Republic of Advanced Process Development Team System LSI Business Samsung Electronics Co. Ltd.

ISBN: (纸本)0780390407

Data retention loss mechanisms in an embedded SONOS memory cell using hot electron programming and hot hole erase are investigated for the first time. After program and erase cycling stress, a reduction in "on" current (Ion) with time at room temperature is observed. This is a serious problem for reliability since the Ion drop results in the narrowing of endurance margin. The increase of local threshold voltage (Vth) resulting from the de-trapping of locally stored holes in the nitride layer above the n+ source junction was found to be responsible for the Ion reduction. Fig.1 shows a schematic cross section of a local SONOS cell. The devices were fabricated using 0.13μm technology with shallow trench isolation (STI) [1]. The thicknesses of the ONO layer are 4nm, 7nm and 11nm, respectively. In the localized SONOS cell, the nitride layer used for charge storage is located only at the source junction side. Fig. 2(a) shows the typical endurance characteristics of our devices. For up to 1,000 cycles, there is no significant change in either the "on" current (Ion) or "off" current (Ioff) and the window margin remains relatively stable. However, as seen in Fig. 2(b), a noticeable decline in "on" current with time is observed once the device is cycled 1,000 times. Fig. 3(a) shows the results of the GIDL current measurements at room temperature with respect to time. Even after one hour, a significant increase in current was observed for more negative Vgs. After 24 hours, the current increases by an order of magnitude. This trend may be explained by the generation of negative fixed charge which originates in the tunnel oxide layer directly above the source junction with additional write/erase cycles [2]. The negative fixed charge trapped in the oxide results in positive charge accumulation at the substrate's surface. This accumulated charge near the n+ junction of the source and directly under the gate overlap causes more severe band-bending. However, it is also important to

关键词： Nonvolatile storage

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The effect of a noble annealing system on nickel silicide formation

The effect of a noble annealing system on nickel silicide fo...

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12th IEEE International Conference on advanced Thermal processing of Semiconductors, RTP 2004

作者： Jung, Sug-Woo Kim, Hyun-Su Jung, Eun-Ji Cheong, Seong-Hwee Yun, Jong-Ho Roh, Kwan-Jong Ku, Ja-Hum Choi, Gil-Heyun Kim, Sung-Tae Chung, U.-In Moon, Joo-Tae Ryu, Byung-Il Process Development Team Semiconductor RandD Center Samsung Electronics Co. Ltd. San #24 Nongseo-Ri Yongin-City Gyeonggi-Do 449-711 Korea Republic of Advanced Process Development Project System LSI Division Samsung Electronics Co. Ltd.

ISBN: (纸本)0780384776

advanced process development project, system lsi Division, Samsung Electronics Co., Ltd. We have investigated the formation of NiSi dependence on three types of annealing systems: annealing systems-I, -II, and -III. The annealing system-I transfers heat by radiation from tungsten halogen lamps in a N2 atmosphere to the wafer and the annealing system-II by conduction from a heated hot plate in vacuum to the wafer. On the other hand, annealing system-III uses a combination of convective and gas phase conductive heat transfer in a N2 atmosphere for wafer heating. Smooth surface and interface morphologies and good electrical properties were obtained for NiSi layers formed using annealing system-III. The wafer heat transfer mechanism from the heat source to wafer is shown to influence the morphological and electrical properties of NiSi. © IEEE.

关键词： Nickel compounds

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High quality high-k MIM capacitor by Ta2O5/HfO 2/Ta2O5 multi-layered dielectric and NH 3 plasma interface treatments for mixed-signal/RF applications

High quality high-k MIM capacitor by Ta2O5/HfO 2/Ta2O5 multi...

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2004 Symposium on Vlsi Technology - Digest of Technical Papers

作者： Jeong, Yong-Kuk Won, Seok-Jun Kwon, Dae-Jin Song, Min-Woo Kim, Weon-Hong Park, Moon-Han Jeong, Joo-Hyun Oh, Han-Su Kang, Ho-Kyu Suh, Kwang-Pyuk Advanced Process Development Project System-LSI Division Samsung Electronics Co. Ltd. San#24 Nongseo-Ri Kiheung-Eup Yongin-City.Kyungki-Do 449-900 Korea Republic of RF Process Architecture Project System-LSI Division Samsung Electronics Co. Ltd. San#24 Nongseo-Ri Kiheung-Eup Yongin-City.Kyungki-Do 449-900 Korea Republic of

Novel high-k MIM capacitor technology for mixed-signal/RF applications has been successfully developed by introducing multilayered high-k dielectric(Ta2O5/HfO22/Ta2O 5) and NH3 plasma electrode-dielectric interfaces treatments. For the first time, we have simultaneously achieved high capacitance of 4fF/um2 and low leakage current of 100nA/cm2 at high temperature of 125°C with ultra low VCC(a=16.9ppm/V2, b=5.2ppm/V) and high Q(∼107 at 2.4GHz and 5.4pF).

关键词： MIM devices

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Lifetime projections and conduction mechanisms for Hafnium based high-k capacitor dielectrics using low thermal budget process

Lifetime projections and conduction mechanisms for Hafnium b...

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Annual International Symposium on Reliability Physics

作者： J.H. Lee J.P. Kim J.-H. Lee Y.-S. Kim H.-J. Lim H.-S. Jung S.J. Doh N.-I. Lee H.-K. Kang Advanced Process Development Project System LSI Business Samsung Electronics Co. Ltd. Yongin-City Kyunggi-Do Korea Adv. Process Dev. Project Samsung Electron. Co. Ltd. Kyunggi-Do South Korea

For the first time, we evaluated the long-term lifetime for Hafnium based high-k dielectrics such as HfO/sub 2/ and HfO/sub 2/-Al/sub 2/O/sub 3/ laminates at 25/spl middot/ /spl middot/ and 125/spl middot/ /spl middot/ in capacitor applications. The extracted Weibull slope of HfO/sub 2/ T/sub BD/ distribution shows thickness dependence to be explained by percolation theory. We demonstrate that elevated operation temperature further accelerates HfO/sub 2/ breakdown than HfO/sub 2/-Al/sub 2/O/sub 3/ laminates, resulting from severe temperature dependent leakage currents due to different conduction mechanisms.

关键词： High K dielectric materials High-K gate dielectrics Capacitors Thermal conductivity Hafnium oxide Laminates Temperature dependence Acceleration Electric breakdown Leakage current

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