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Effect of Dielectric Materials on Stress-Induced Damage Modes in Damascene Cu Lines

MRS Online Proceedings Library 2004年第1期795卷 403-408页

作者： Jong-Min Paik Hyun Park Ki-Chul Park Young-Chang Joo School of Materials Science and Engineering Seoul National University Seoul Korea Advanced Process Development Project Team System LSI Division Samsung Electronics Co. Ltd. Young-In City Gyeonggi-Do Korea

Various low-k materials are being pursued as dielectric materials for future interconnects. However, poor thermo-mechanical properties of low-k materials cause tremendous reliability concerns, thus the proper materials for integration with Cu are not suggested yet. In this study, the line width and spacing dependence of damascene Cu lines embedded by TEOS and low-k materials (CORAL) was analyzed using x-ray diffraction. Generally, the hydrostatic stress of Cu/TEOS was greater than that of Cu/CORAL, while the opposite for von-Mises stress. Using a three-dimensional finite analysis (LEA), the effect of low-k materials on the stress and its distribution in via-line structures of dual damascene Cu interconnects was studied. In the case of Cu/TEOS, the hydrostatic stress was concentrated at the via and on the top of the lines, where it was suspected that the void would nucleate. On the other hand, in the via-line structures integrated with organic low-k materials, large von-Mises stress was maintained in the via. Therefore, the deformation of via, rather than voiding, may be the main failure mode in the interconnects with low-k materials.

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Effect of mechanical strength and residual stress of dielectric capping layer on electromigration performance in Cu/low-k interconnects

Effect of mechanical strength and residual stress of dielect...

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International Electron Devices Meeting (IEDM)

作者： K.-W. Lee H.J. Shin Y.J. Wee T.K. Kim A.T. Kim J.H. Kim S.M. Choi B.S. Suh S.J. Lee K.-K. Park J.W. Hwang S.W. Nam Y.J. Moon J.E. Ku H.J. Lee M.Y. Kim I.H. Oh J.Y. Maeng I.R. Kim J.E. Lee A.M. Lee W.-H. Choi S.J. Park N.I. Lee H.-K. Kang G.P. Suh Advanced Process Development Team System LSI Business Advanced Process Development Team System LSI Business Samsung Electronics Company Limited Yongin si Kyunggi South Korea CAE Team Memory Business Samsung Electronics Company Limited Yongin si Kyunggi South Korea CAE Team Samsung Electronics Co. Ltd Youngin-City Kyunggi-Do KOREA

We present the effect of mechanical strength and residual stress of dielectric barrier on electromigration performance in Cu/low-k interconnects. It has been discovered that mechanical strength and residual stress of dielectric capping layer have a great role on EM performance. The use of mechanically strong dielectric capping material with high residual compressive stress in Cu/low-k interconnects improves a structural confinement of Cu line. Also, it helps tensile stress level decrease near via bottom and compressive stress level increase at Cu beneath SiCN along Cu line. Reduction of tensile stress at via bottom would effectively suppress void nucleation and growth. Moreover, increase of compressive stress in Cu beneath SiCN alleviates Cu migration through that pathway, leading to a longer lifetime of interconnect component.

关键词： Residual stresses Dielectrics Electromigration Copper Compressive stress Etching Atomic layer deposition Mechanical factors Tensile stress Chemicals

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Editor's note

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IEEE Transactions on Visualization and Computer Graphics 2004年第1期10卷 1-1页

作者： D.S. Ebert Advanced Process Development Project System LSI Business Samsung Electronics Co. Ltd Yongin Kyunggi-Do Korea

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Alleviating Electromigration Through Re-Engineering the Interface between Cu & Dielectric-Diffusion-Barrier in 90 nm Cu/SioC (k=2.9) Device

Alleviating Electromigration Through Re-Engineering the Inte...

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IEEE International Electron Devices Meeting

作者： Wee, Young Jin Lee, Soo Geun Song, Won Sang Lee, Kyoung-Woo Lee, Nam Hyung Ku, Ja Eung Park, Ki-Kwan Lee, Seung Jin Kim, Jae Hak Chung, Joo Hyuk Shin, Hong Jae Hah, Sang Rok Kang, Ho-Kyu Suh, Gwang Pyuk Advanced Process Development Team System LSI Business Samsung Electronics Co. Ltd. San#24 Nongseo-Ri Kiheung-Eup Youngin-City Kyunggi-Do 449-711 Korea Republic of

Despite the initial success in integrating 90 nm Cu/SiOC (k=2.9) device using the HSQ via-filler scheme, the reliability issues remain. By correlating EM with the moisture blocking capability of the dielectric-diffusion-barrier, we target the factors contributing to the moisture blockage, namely, the N and H-content within SiC. Consequently, increasing the N/H ratio in the SiCN film, we demonstrated a significant enhancement in EM reliability.

关键词： Dielectric materials

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Thermally Robust Ta-Doped Ni SALICIDE process Promising for Sub-50nm CMOSFETs

Thermally Robust Ta-Doped Ni SALICIDE Process Promising for ...

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2003 Symposium on Vlsi Technology

作者： Sun, M.C. Kim, M.J. Ku, J.-H. Roh, K.J. Kim, C.S. Youn, S.P. Jung, S.-W. Choi, S. Lee, N.I. Kang, H.-K. Suh, K.P. Advanced Process Development Project System LSI Division Samsung Electronics Co. Ltd. San#24 Yongin-City Gyeonggi-Do 449-900 Korea Republic of Process Development Team Memory Division Samsung Electronics Co. Ltd. San#24 Yongin-City Gyeonggi-Do 449-900 Korea Republic of

For sub-50nm device application, Self-Aligned siLICIDE (SALICIDE) process by NiTa alloy has been developed for the first time. Use of NiTa-alloy makes nickel suicide on 50nm gate thermally-robust up to 600°C during device febrication. NiTa SALICIDE process can also achieve excellent value and distribution of sheet resistance on 30nm gate as well as low junction leakage current compared to Co SALICIDE. Furthermore, the drive current of PMOS is greatly increased. As a result, high-performance 90nm MOSFETs is successfully integrated with NiTa SALICIDE process.

关键词： MOSFET devices

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Ultimate Solution for Low Thermal Budget Gate Spacer and Etch Stopper to Retard Short Channel Effect in Sub-90nm Devices

Ultimate Solution for Low Thermal Budget Gate Spacer and Etc...

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2003 Symposium on Vlsi Technology

作者： Yang, Jong-Ho Park, Jae-Eun Lee, Joo-Won Chu, Kang-Soo Ku, Ja-Hum Park, Moon-Han Lee, Nae-In Kang, Hee-Sung Oh, Myung-Hwan Lee, Jun-Ha Kang, Ho-Kyu Suh, Kwang-Pyuk Advanced Process Development Project System LSI Division Samsung Electronics Co. Ltd. San#24 Nongseo-Ri Yongin-City Kyunggi-Do 449-711 Korea Republic of Technology Development System LSI Division Samsung Electronics Co. Ltd. Yongin-City Kyunggi-Do Korea Republic of CAE Team Memory Division Samsung Electronics Co. Ltd. Yongin-City Kyunggi-Do Korea Republic of

For the first time, by employing low thermal budget processes of ALD SiO2 and ALD SiN as gate spacer and suicide blocking layer, the short channel effects of CMOSFETs are significantly suppressed. Using the ALD SiO: and ALD SiN processes, we achieved excellent roll-off characteristics of threshold voltage in PMOS, which results in 10% increase of drive current and 15% decrease of inverter delay time. Furthermore, gate oxide reliability and static noise margin of 6T-SRAM bit cell with ALD SiO2/SiN processes are comparable to those with conventional high temperature CVD SiO 2/SiN processes. In conclusion, ALD SiO2 and ALD SiN processes of extremely low thermal budget are successfully implemented to sub-90nm CMOSFETs.

关键词： Gates (transistor)

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Characteristics of ALD-TaN thin films using a novel precursors for copper metallization

Characteristics of ALD-TaN thin films using a novel precurso...

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2003 IEEE International Interconnect Technology Conference, IITC 2003

作者： Choi, Kyung In Kim, Byung Hee Lee, Sang Woo Lee, Jong Myeong Song, Won Sang Choi, Gil Heyun Chung, U-In Moon, Joo Tae Process Development Team Semiconductor R and D Center Samsung Electronics Co. Ltd. Yongin-City Kyungki-Do449-711 Korea Republic of Advanced Process Development Project System-LSI Division Samsung Electronics Co. Ltd. San #24 Nongseo-Ri Kiheung-Eup Yongin-City Kyungki-Do449-711 Korea Republic of

ISBN: (纸本)0780377974

ALD-TaN thin films derived from tert-buthyIimidotrisdiethyl-amidotantalum (TBTDET) and tert-amylimidotrisdim-ethylamidotantalum (TAIMATA) precursors for the diffusion barrier in Cu interconnects were developed. The deposition rate of the ALD-TaN process was saturated at 0.4 Å/cycle in a temperature range between 200°C and 250°C with TBTDET and at 0.2 Å/cycle in a temperature range between 150°C and 200°C with TAIMATA. Both precursors provided roughly comparable film properties such as not only excellent conformality but also composition and structure characterized by XPS and XRD, respectively. ALD-TaN films obtained from above precursors yield low via resistance in aluminum interconnects. However, relatively high via resistance was resulted upon Cu integration as compared to PVD-TaN and Al metallization. The superior diffusion barrier characteristic on Cu metallization was observed with ALD-TaN by BTS result in comparison to the conventional PVD-TaN. © 2003 IEEE.

关键词： Temperature distribution

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Highly manufacturable SONOS non-volatile memory for the embedded SoC solution

Highly manufacturable SONOS non-volatile memory for the embe...

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Symposium on Vlsi Technology

作者： J.-H. Kim I.W. Cho G.J. Bae S.S. Kim K.C. Kim S.H. Kim K.W. Koh N.I. Lee H.-K. Kang K.-P. Suh S.T. Kang M.K. Seo S.H. Lee M.C. Kim I.S. Park Advanced Process Development Project Advanced Process Development Project Samsung Electronics Company Limited Yongin si Kyunggi South Korea EFL Process Architecture Samsung Electronics Company Limited Yongin si Kyunggi South Korea EFL Process Architecture Memory Core System LSI Business Process Development Team Memory Business Samsung Electronics Co. Ltd Yongin-Si Kyunggi-Do Korea

ISBN: (纸本)489114033X

A new Local SONOS structure has been proposed for an embedded NVM cell in 0.13 /spl mu/m standard CMOS logic process. The localized storage silicon nitride layer of Local SONOS cell provides the essential properties for the embedded NVM such as the complete erase, low program current, and high on cell current from the low threshold voltage. The entire embedded memory solution has been realized with 0.276 /spl mu/m/sup 2/ Local SONOS NVM cell, which has 20 /spl mu/s program and 2 ms erase speed under 5.5 V bias condition, and good reliability without the special algorithms and cell array modifications.

关键词： Manufacturing SONOS devices Nonvolatile memory Threshold voltage CMOS process CMOS logic circuits Programmable logic arrays Logic arrays Large scale integration Standards development

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Highly Manufacturable SONOS Non-Volatile Memory for the Embedded SoC Solution

Highly Manufacturable SONOS Non-Volatile Memory for the Embe...

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2003 Symposium on Vlsi Technology

作者： Kim, J.-H. Cho, I.W. Bae, G.J. Kim, S.S. Kim, K.C. Kim, S.H. Koh, K.W. Lee, N.I. Kang, H.-K. Suh, K.-P. Kang, S.T. Seo, M.K. Lee, S.H. Kim, M.C. Park, I.S. Advanced Process Development Project San #24 Nongseo-Ri Kiheung-Eup Yongin-Si Kyunggi-Do 449-900 Korea Republic of EFL Process Architecture San #24 Nongseo-Ri Kiheung-Eup Yongin-Si Kyunggi-Do 449-900 Korea Republic of Memory Core System LSI Business San #24 Nongseo-Ri Kiheung-Eup Yongin-Si Kyunggi-Do 449-900 Korea Republic of Process Development Team Memory Business Samsung Electronics Co. Ltd. San #24 Nongseo-Ri Kiheung-Eup Yongin-Si Kyunggi-Do 449-900 Korea Republic of

A new Local SONOS structure has been proposed for an embedded NVM cell in 0.13 μm standard CMOS logic process. The localized storage silicon nitride layer of Local SONOS cell provides the essential properties for the embedded NVM such as the complete erase, low program current, and high on cell current from the low threshold voltage. The entire embedded memory solution has been realized with 0.276 μm2 Local SONOS NVM cell, which has 20 μs program and 2 ms erase speed under 5.5V bias condition, and good reliability without the special algorithms and cell array modifications.

关键词： Nonvolatile storage

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Novel Plasma Enhanced Atomic Layer Deposition Technology for High-k Capacitor with EOT of 8 Å on Conventional Metal Electrode

Novel Plasma Enhanced Atomic Layer Deposition Technology for...

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2003 Symposium on Vlsi Technology

作者： Won, Seok-Jun Jeong, Yong-Kuk Kwon, Dae-Jin Park, Moon-Han Kang, Ho-Kyu Suh, Kwang-Pyuk Kim, Hong-Ki Ka, Jae-Hwan Yun, Kwan-Young Lee, Duck-Hyung Kim, Dae-Youn Yoo, Yong-Min Lee, Choon-Soo Advanced Process Development Project MML PA Project San#24 Nongseo-Lee Kiheung-Eup Yongin-City Kyungki-Do 449-900 Korea Republic of System-LSI Division Samsung Electronics Co. Ltd. Genitech Co. Ltd. San#24 Nongseo-Lee Kiheung-Eup Yongin-City Kyungki-Do 449-900 Korea Republic of

We have developed a plasma enhanced atomic layer deposition(PEALD) technology for high-k dielectrics such as Al2O3, Ta 2O5 and HfO2. Film quality and throughput of PEALD are far superior to that of ALD which has been spotlighted as a deposition technology for next generation semiconductor devices. We have obtained a extremely low equivalent oxide thickness(EOT) of 8 Å from HfO2 film, which has not been reported in conventional metal-based memory capacitors up to now. It was confirmed that PEALD-Al2O 3 and Ta2O5 films are superior to those using any other deposition techniques and very useful as system-on-Cnip(SoC) capacitors.

关键词： Dielectric films

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