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Practical next generation solution for stand-alone and embedded DRAM capacitor

Practical next generation solution for stand-alone and embed...

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Symposium on Vlsi Technology

作者： Jong-Ho Lee Jung-Hyoung Lee Yun-Seok Kim Hyung-Seok Jung Nae-In Lee Ho-Kyu Kang Kwang-Pyuk Suh Advanced Process Development Project Samsung Electronics Company Limited Yongin si Kyunggi South Korea Advanced Process Development Project System LSI Business Samsung Electronics Company Limited Yongin si Kyunggi South Korea

ISBN: (纸本)078037312X

For the first time, MIS capacitors with HfO/sub 2/-Al/sub 2/O/sub 3/ laminate are successfully demonstrated. The effective oxide thickness (EOT) of 21 /spl Aring/ with an acceptably low leakage current has been achieved for a cylinder-type MIS capacitor. The EOT of 21 /spl Aring/ is the smallest value reported for MIS capacitors with TiN electrodes regardless of dielectric material. We have confirmed the feasibility of reducing EOT in spite of the simple process without a pre-deposition treatment. HfO/sub 2/-Al/sub 2/O/sub 3/ laminate is also useful for SIS capacitors and can satisfy the needs of MIM capacitors for the next generation without changing electrode material.

关键词： Random access memory Laminates MIM capacitors Leakage current Hafnium oxide High-K gate dielectrics Electrodes Dielectric materials High K dielectric materials Dielectric constant

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A new double-layered structure for mass-production-worthy CMOSFETs with poly-SiGe gate

A new double-layered structure for mass-production-worthy CM...

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Symposium on Vlsi Technology

作者： Hwa Sung Rhee Jung Il Lee Sang Su Kim Geum Jong Bae Nae-In Lee Do Hyung Kim Jung In Hong Ho-Kyu Kang Kwang Pyuk Suh Advanced Process Development Project System LSI Business Yongin si Kyunggi South Korea Samsung Electronics Company Limited Yongin si Kyunggi South Korea

ISBN: (纸本)078037312X

A new double-layered structure of poly-Si/SiGe gate has been proposed to improve the current performance of CMOSFETs and the reproducibility of devices. The double-layered poly-Si/SiGe stack has small-sized (columnar) grains in the lower poly-SiGe layer and large-sized grains in the upper poly-Si layer. The new structure can suppress Ge diffusion into the upper poly-Si layer during CMOS process, resulting in enhanced current performance and better sheet resistance distribution to meet gate height scaling requirements of sub-0.1 /spl mu/m CMOSFETs. A mass productive 8 Mbit SRAM with both the smallest cell size and enhanced operation speed by 20% was successfully fabricated using the proposed poly-SiGe gate structure.

关键词： CMOSFETs Silicon germanium Germanium silicon alloys CMOS process Reproducibility of results Grain boundaries Random access memory Fluctuations Large scale integration Boron

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Cost-effective "BARC/resist-via-fill free" integration technology for 0.13 /spl mu/m Cu/low-k

Cost-effective "BARC/resist-via-fill free" integration techn...

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International Electron Devices Meeting (IEDM)

作者： Soo-Geun Lee Kyoung-Woo Lee Il-Goo Kim Wan-Jae Park Young-Jin Wee Won-Sang Song Jae-Hak Kim Seung-Jin Lee Hyeok-Sang Oh Yong-Tak Lee Joo-Hyuk Chung Ho-kyu Kang Kwang-Pyuk Suh Advanced Process Development Team System LSI Business Samsung Electronics Company Limited Yongin si Gyeonggi South Korea

ISBN: (纸本)0780374622

Demonstrates the first successful integration scheme free of BARC/resist via-fill that not only significantly simplifies the overall process complexity, but also reduces cost and process instabilities by employing an OSG (k=2.9)/ HDP-FSG dual ILD structure in conjunction with our proprietary plasma induced polymeric etch stopper (PIPS) in a 7-metal level 0. 13 /spl mu/m design node. The via poisoning problem and low selectivity of etch stopper were overcome by optimizing ILD structure and PIPS etch process. The electrical characteristics and reliability results indicate that the current integration scheme is highly manufacturable.

关键词： Etching Resists Silicon carbide Costs Polymer films Plasma applications Plasma materials processing Dielectrics Optical films Plasma chemistry

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Mass-productive ultra-low temperature ALD SiO2 process promising for sub-90 nm memory and logic devices

Mass-productive ultra-low temperature ALD SiO2 process promi...

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2002 IEEE International Devices Meeting (IEDM)

作者： Park, Jae-Eun Ku, Ja-Hum Lee, Joo-Won Yang, Jong-Ho Chu, Kang-Soo Lee, Seung-Hwan Park, Moon-Han Lee, Nae-In Kang, Ho-Kyu Suh, Kwang-Pyuk Cho, Byoung-Ha Kim, Byoung-Chul Shin, Cheol-Ho Advanced Process Development Project System LSI Division Samsung Electronics Co. Ltd. San #24 Nongseo-Ri Kiheung-Eup Yongin-City Kyunggi-Do 449-711 Korea Republic of Moohan Inc. #5-1 Chaam-Dong Chonan-City Chungchongnam-Do 330-200 Korea Republic of

For the first time, ultra-low temperature ALD SiO2 is successfully developed and applied on W/WN/poly-Si stack gate as a dual spacer for the enhancement of data retention time. ALD SiO2 deposition is performed at 75 °C using HCD and H2O as precursors and pyridine as a catalyst. Using ALD SiO2 process, SiO2 layer is deposited on W/WN/poly-Si stack gate without W oxidation. The gate resistances of W/WN/poly-Si stack gate do not exhibit any difference between SiN single spacer and SiO2/SiN dual spacer schemes, which indicates that W oxidation does not occur during the ALD SiO2 deposition for the formation of dual spacer. Conclusively, the significant improvement(>50%) of data retention time is achieved by employing SiO2/SiN dual spacer at W/WN/poly-Si stack gate in 130nm DRAM device. In addition, excellent short channel characteristics of Vth is identified by applying low temperature ALD SiO2 layer as a dual spacer on sub-100 nm SRAM device.

关键词： Semiconductor storage

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Improved current performance of CMOSFETs with nitrogen incorporated HfO2-Al2O3 laminate gate dielectric

Improved current performance of CMOSFETs with nitrogen incor...

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2002 IEEE International Devices Meeting (IEDM)

作者： Jung, Hyung-Seok Kim, Yun-Seok Kim, Jong Pyo Lee, Jung Hyoung Lee, Jong-Ho Lee, Nae-In Kang, Ho-Kyu Suh, Kwang-Pyuk Ryu, Hyuk Ju Oh, Chang-Bong Kim, Young-Wug Cho, Kyung-Hwan Baik, Hion-Suck Chung, Young Su Chang, Hyo Sik Moon, Dae Won Advanced Process Development Project System LSI Business Samsung Electronics Co. Ltd. San 24 Nongseo-Ri Kiheung-Eup Yongin-City Kyunggi-Do 449-711 Korea Republic of AE Center Samsung Advd. Inst. of Technology Gyungyi-Do Korea Republic of Nano Surface group Korea Res. Inst. of Std. and Science Taejon Korea Republic of

For the first time, we integrated poly-Si gate CMOSFETs with nitrogen incorporated HfO2-Al2O3 laminate (HfAlON) as gate dielectrics. Both low gate leakage currents (0.1mA/cm2 at Vg=+1.0V) and low EOT (15.6 Å) sufficiently satisfy the specifications (EOT=12∼20Å, Jg=2.2mA/cm2) estimated by ITRS for low power applications. By in-situ 3 step post-deposition annealing, approximately 17 at.% nitrogen is incorporated at the HfAlON/Si interface. In-situ 3 step post-deposition annealing decreases metallic Hf bonding, which exists at the HfO2-Al2O3 laminate/Si interface. As a result, we can suppress C-V hysteresis and improve current performance. Finally, well-behaved 100 nm CMOSFET devices are achieved. The measured saturation currents at 1.2V Vdd are 585μA/μm (Ioff=10nA/μm) for nMOSFET and 265μA/μm (Ioff=10nA/ μm) for pMOSFET, which are approximately 80% of those of nitrided SiO2. In terms of Ion-Ioff characteristics of n/pMOSFETs, these are the best current performance compared with previous reports for the poly-Si gate CMOSFETs with high-k gate dielectrics.

关键词： MOSFET devices

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Mass-productive ultra-low temperature ALD SiO/sub 2/ process promising for sub-90 nm memory and logic devices

Mass-productive ultra-low temperature ALD SiO/sub 2/ process...

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International Electron Devices Meeting (IEDM)

作者： Jae-Eun Park Ja-Hum Ku Joo-Won Lee Jong-ho Yang Kang-Soo Chu Seung-Hwan Lee Moon-Han Park Nae-In Lee Ho-Kyu Kang Kwang-Pyuk Suh Byoung-Ha Cho Byoung-Chul Kim Cheol-Ho Shin Advanced Process Development Project System LSI Division Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Moohan Inc. Chonan Chungcheongnam South Korea

ISBN: (纸本)0780374622

For the first time, ultra-low temperature ALD SiO/sub 2/ is successfully developed and applied on W/WN/poly-Si stack gates as a dual spacer for the enhancement of data retention time. ALD SiO/sub 2/ deposition is performed at 75/spl deg/C using HCD and H/sub 2/O as precursors and pyridine as a catalyst. Using the ALD SiO/sub 2/ process, SiO/sub 2/ layers are deposited on W/WN/poly-Si stack gates without W oxidation. The gate resistances of the W/WN/poly-Si stack gates do not exhibit any difference between SiN single spacer and SiO/sub 2//SiN dual spacer schemes, which indicates that W oxidation does not occur during the ALD SiO/sub 2/ deposition for dual spacer formation. Conclusively, the significant improvement (>50%) of data retention time is achieved by employing SiO/sub 2//SiN dual spacers at W/WN/poly-Si stack gates in a 130 nm DRAM device. In addition, excellent short channel characteristics of Vth are identified by applying a low temperature ALD SiO/sub 2/ layer as a dual spacer on sub-100 nm SRAM devices.

关键词： Temperature Logic devices Oxidation Random access memory Silicon compounds Atomic layer deposition Annealing Rough surfaces Surface roughness Atomic measurements

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Mass production worthy HfO2-Al2O3 laminate capacitor technology using Hf liquid precursor for sub-100 nm DRAMs

Mass production worthy HfO2-Al2O3 laminate capacitor technol...

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2002 IEEE International Devices Meeting (IEDM)

作者： Lee, Jung-Hyoung Kim, Jong Pyo Lee, Jong-Ho Kim, Yun-Seok Jung, Hyung-Seok Lee, Nae-In Kang, Ho-Kyu Suh, Kwang-Pyuk Jeong, Mun-Mo Hyun, Kyu-Taek Baik, Hion-Suck Chung, Young Su Liu, Xinye Ramanathan, Sasangan Seidel, Tom Winkler, Jerald Londergan, Ana Kim, Hae Young Ha, Jung Min Lee, Nam Kyu Advanced Process Development Project System LSI Business Samsung Electronics Co. Ltd. San #24 Nongseo-Ri Kiheung-Eup Yongin-City Kyunggi-Do 449-711 Korea Republic of DRAM PA Team Memory Business Samsung Electronics Suwon Korea Republic of AE Center Samsung Adv. Inst. of Technology Gyungyi-Do Korea Republic of Genus Inc. 1139 Karlstad Dr. Sunnyvale CA 94089 United States

For the first time, we successfully demonstrated MIS capacitor with ALD (Atomic Layer Deposition) grown HfO2-Al2O3 laminate film using Hf liquid precursor (Hf(NEtMe)4) with EOT of 22.5 Å and acceptable leakage currents (1.0fA/cell at 1.65 V) which is comparable to the smallest reported value. Advantages of Hf(NEtMe)4 liquid precursor for DRAM capacitor dielectric are excellent step coverage (94% on high aspect ratio(>40:1)) and reasonable throughput (over two times higher than that of HfCl4 solid precursor). This study will provide practical solution for chip-making industry in terms of mass production worthy process for sub-100 nm DRAM capacitor.

关键词： MIS devices

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Improved current performance of CMOSFETs with nitrogen incorporated HfO2-Al2O3 laminate gate dielectric

Improved current performance of CMOSFETs with nitrogen incor...

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International Electron Devices Meeting (IEDM)

作者： Hyung-Seok Jung Yun-Seok Kim Jong Pyo Kim Jung Hyoung Lee Jong-Ho Lee Nae-In Lee Ho-Kyu Kang Kwang-Pyuk Suh Hyuk Ju Ryu Chang-Bong Oh Young-Wug Kim Kyung-Hwan Cho Hion-Suck Baik Young Su Chung Hyo Sik Chang Dae Won Moon Advanced Process Development Project Samsung Electronics Co. Ltd. Yongin-City Kyunggi-Do Korea Technology Development Samsung Electronics Co. Ltd. South Korea Technology Development Samsung Electronics Co. Ltd. Kl Manufacturing Team Samsung Electronics Co. Ltd. Advanced Process Development Project System LSI Business Samsung Electronics Company Limited Yongin si Gyeonggi South Korea AE Center Samsung Advanced Institute of Technology South Korea Nano Surface group Korea Research Institute of Standard and Science South Korea

ISBN: (纸本)0780374622

For the first time, we integrated poly-Si gate CMOSFETs with nitrogen incorporated HfO/sub 2/-Al/sub 2/O/sub 3/ laminate (HfAlON) as gate dielectrics. Both low gate leakage currents (0.1 mA/cm/sup 2/ at V/sub g/=+1.0 V) and low EOT (15.6 /spl Aring/) sufficiently satisfy the specifications (EOT=12/spl sim/20 /spl Aring/, J/sub g/=2.2 mA/cm/sup 2/) estimated by ITRS for low power applications. By in-situ 3 step post-deposition annealing, approximately 17 at.% nitrogen is incorporated at the HfAlON/Si interface. In-situ 3 step post-deposition annealing decreases metallic Hf bonding, which exists at the HfO/sub 2/-Al/sub 2/O/sub 3/ laminate/Si interface. As a result, we can suppress C-V hysteresis and improve current performance. Finally, well-behaved 100 nm CMOSFET devices are achieved. The measured saturation currents at 1.2 V V/sub dd/ are 585 /spl mu//spl Aring///spl mu/m (I/sub off/= 10 nA//spl mu/m) for nMOSFET and 265 /spl mu/A//spl mu/m (I/sub off/=10 nA//spl mu/m) for pMOSFET, which are approximately 80% of those of nitrided SiO/sub 2/. In terms of I/sub on/-I/sub off/ characteristics of n/pMOSFETs, these results represent the best current performance compared with previous reports for poly-Si gate CMOSFETs with high-k gate dielectrics.

关键词： CMOSFETs Nitrogen Hafnium oxide MOSFET circuits Laminates Annealing Dielectrics Leakage current Bonding Capacitance-voltage characteristics

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