检索结果-内蒙古大学图书馆

2011 IEEE International Conference on Integrated Circuit Design and technology, ICICDT 2011

作者： Mitani, Y. Fukatsu, S. Hagishima, D. Matsuzawa, K. Advanced LSI Technology Laboratory Corporate R and D Center Toshiba Corporation Yokohama 235-8522 Japan Device Process Development Center Toshiba Corporation Toshiba Semiconductor Company Japan

ISBN: (纸本)9781424490202

Channel hot-carrier (CHC) degradation becomes more critical as the channel length is reduced. In general, CHC degradation is evaluated using DC stress applying both gate and drain bias. However, in the case of p-channel MOSFETs, negative bias temperature instabilities (NBTI) also degrades threshold voltage (VTH) and saturation drain current (Isat) under DC stress applying gate bias. Therefore, CHC degradation might include the NBTI component, which would lead to over-estimate the CHC degradation. Therefore, a separation of the BTI component from CHC degradation is necessary to predict device lifetime more accurately. In this study, a simple separation method of NBTI and CHC component from CHC test data is proposed, focusing on the recovery phenomenon, which is a distinctive behavior of NBTI. © 2011 IEEE.

关键词： Negative bias temperature instability

来源：评论

学校读者我要写书评

暂无评论

Design intent application to tolerance-based manufacturing system

Design intent application to tolerance-based manufacturing s...

引用

作者： Kobayashi, Sachiko Tanaka, Satoshi Kyoh, Suigen Maeda, Shimon Kajiwara, Masanari Inoue, Soichi Nakamae, Koji Toshiba Corporation Advanced Lithography Process Technology Department Device Process Development Center 8 Shinsugita-cho Isogo-ku Yokohama City Kanagawa-Pref 235-8522 Japan Osaka University Graduate School of Information Science and Technology 2-1 Yamada-oka Suita-shi Osaka Japan

Continuous shrinkage of the design rule in large-scale integrated circuit devices brings about greater difficulty in the manufacturing process. The keys to meeting small process margin are adequate extraction of critical dimension tolerance for each object, considering design intent in terms of electrical behavior, and assigning the tolerance for each process step. However, once the design data are converted to layout data and signed off, most of the design intent is abandoned and unrecognized in the process phase. Thus, uniform and redundant tolerance is used, and therefore, excess tolerance is assigned for some layouts. To solve the problem described above, a tolerance-based manufacturing system utilizing flexible layout-dependent speculation derived from design intent has been discussed. Using a 40-nm node test chip, electrically critical spots, such as timing, cross-talk noise, electromigration, with small margins are extracted, assigned to the physical layout, and utilized in the manufacturing process. The flow is applicable for optical proximity effect correction (OPC) turnaround time reduction, optimization of OPClithography compliance check (LCC) specification, and failure-analysis acceleration. Consequently, a design-intent-aware manufacturing system is promising for realizing proper process specifications and computational cost reduction, in addition to yield enhancement. © 2011 Society of Photo-Optical Instrumentation Engineers (SPIE).

关键词： Specifications

来源：评论

学校读者我要写书评

暂无评论

advanced floating gate CD uniformity control in the 75nm node NOR flash memory

Advanced floating gate CD uniformity control in the 75nm nod...

引用

IEEE/SEMI Conference and Workshop on advanced Semiconductor Manufacturing

作者： Sheng-Yuan Chang Yu-Chung Chen An Chyi Wei Hong-Ji Lee Nan-Tzu Lian Tahone Yang Kuang-Chao Chen Chih-Yuan Lu Technology Development Center Advanced Module Process Development Division Macronix International Company Limited Hsinchu Taiwan

This paper describes the advanced control technology of critical dimension uniformity (CDU) by flash gate stack etch process. We have investigated the effective way of utilizing Tri-layer approach, which not only reduces the influence of topology step-height but also improves the range of ECD within die from 17.6nm to 4.9nm. Moreover, the influence of Etcher design on ECD variation becomes larger as the cell transistor size becomes smaller. The etch chamber effect is minimized by developing CF 4 /CHF 3 /N 2 plasma at 15mTorr pressure that provides better ECD uniformity within wafer.

关键词： Plasmas Logic gates Etching Polymers Flash memory Chemistry

来源：评论

学校读者我要写书评

暂无评论

Post etch killer defect characterization and reduction in a self-aligned double patterning technology

Post etch killer defect characterization and reduction in a ...

引用

IEEE/SEMI Conference and Workshop on advanced Semiconductor Manufacturing

作者： Hong-Ji Lee Sun-Yi Lin I-Ting Lin Kuo-Liang Wei Sheng-Yuan Chang Nan-Tzu Lian Tahone Yang Kuang-Chao Chen Chih-Yuan Lu Technology Development Center Advanced Module Process Development Division Macronix International Company Limited Hsinchu Taiwan

This paper identifies post etch killer defects, e.g., core bridging, small particle and tiny bridging, and investigates the possible solutions in a SADP module. Among the killer defect adders, core bridging and small particle are commonly observed after the oxide core removal by BOE. Core bridging adder is a carbon-containing polymeric by-product during nitride spacer open; by introducing additional diluted HF (DHF) treatment could effectively eliminate such bridging adder. Small particle adder is found to peel from the poly-Si hard mask-1 (HM1) damaged location, where is eroded during the wafer backside cleaning. It is useful for suppressing the formation of small particle by skipping the wafer backside cleaning process. Tiny bridging adder is block of etched poly-Si HM1 causing short between lines. One possibility of blocked etch adder creating is the fine micromasking formed on the opening of BARC during poly-Si HM1 etching. The effective suppression of tiny bridging adder is using high energetic F-/O-radicals to break through the micromasking in the poly-Si HM1 patterning. The reductions of above killer defects successfully boost up the sorting yield in our 45 nm charge-trapping flash memory.

关键词： Adders Etching Plasmas Cleaning Flash memory Inspection Polymers

来源：评论

学校读者我要写书评

暂无评论

Grain Engineering Approaches for High-Performance Polysilicon Thin-Film Transistor Fabrication

引用

MRS Online Proceedings Library 2011年第1期508卷 55-65页

作者： G. K. Giust T. W. Sigmon Memory Technology & Integration LSI Logic Santa Clara USA Advanced Process and Development Group Lawrence Livermore National Laboratory Livermore USA

Using an approach we call “grain engineering,” we discuss several techniques to control grain growth during excimer laser annealing, to create low-defect density polysilicon films. By adjusting of laser parameters, for example, we obtain polysilicon films with grain sizes of more than 9 µm, without substrate heating. These high-quality films are used in the fabrication of low-temperature unhydrogenated polysilicon thin-film transistors (TFT’s) yielding mobilities of > 260 cm2/Vs and on/off current ratios > 107. We investigate the laser recrystallization of “prepatterned” films as another technique of grain engineering. We find the performance of TFT’s fabricated in active areas that are prepatterned before laser recrystallization is dramatically improved compared to those TFT’s fabricated from the laser recrystallization of blanket polysilicon films. A novel “recessed” structure is also examined as a new grain engineering tool. By depositing a blanket silicon film on a patterned oxide layer on a heat sink, the heat flow through the continuous silicon film may be controlled during laser recrystallization to simultaneously produce adjacent regions of remarkably different grain microstructure.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Design intent utilization for lithography compliance check and layout refinement to improve manufacturability

Design intent utilization for lithography compliance check a...

引用

IEEE International Symposium on Semiconductor Manufacturing

作者： Sachiko Kobayashi Atsuhiko Ikeuchi Kazunari Kimura Toshiya Kotani Satoshi Tanaka Suigen Kyoh Shimon Maeda Soichi Inoue Advanced Lithography Process Technology Department Device Process Development Center Corporate Research & Development Center Toshiba Corporation Japan Design Methodology Development Group Design Technology Development Department Analog & Imaging Ic Division Toshiba Corporation Semiconductor Company Japan

A collection of slides from the authors conference presentation about the design intent utilization for lithography compliance check and layout refinement to improve manufacturability is presented.

关键词： Lithography Timing Data mining Loss measurement Wires Design methodology

来源：评论

学校读者我要写书评

暂无评论

Retention characteristics of Pb(Zr, Ti)O3 films deposited by various methods for high-density non-volatile memory

引用

MRS Online Proceedings Library (OPL) 2011年第1期748卷 U4.1-U4.1页

作者： Sangmin Shin Mirko Hofmann Yong Kyun Lee Choong Rae Cho June Key Lee Youngsoo Park Kyu Mann Lee Yoon Jong Song Materials & Devices Laboratory Samsung Advanced Institute of Technology Suwon 440–600 Korea Process development team Samsung Electronics Yongin 449–900 Korea

Retention loss is a significant issue for an application of ferroelectric thin films to high-density non-volatile memory devices. We investigated the polarization retention characteristics of ferroelectric Pb(Zr,Ti)O3 (PZT) thin films which were fabricated on Pt/IrO2/Ir substrates by different deposition methods. In thermally-accelerated retention failure tests, Pb(Zr,Ti)O3 (PZT) films which were prepared by a chmeical solution deposition (CSD) method showed rapid decay of retained polarization charges as the films became thinner down to 1000 Å, while the films which were grown by metal organic chemical vapor deposition (MOCVD) showed relatively large nonvolatile charges at the same thickness. We concluded that in the CSD-grown films, the relatively large interfacial passive layer compared with the MOCVD-grown films had an unfavorable effect on retention behavior. We observed the existence of such interfacial layers by extrapolation of the total capacitance with thickness of the films and the capacitance of this layer was larger in MOCVD-grown films. It means that the possibility of the accumulation of space charges at the interface was reduced, so that less imprint and less retention loss could be observed in the MOCVD-grown films.

关键词： PZT MOCVD CSD(sol-gel) FRAM retention loss ferroelectric thin film.

来源：评论

学校读者我要写书评

暂无评论

Energy analysis of CaCO 3 calcination with CO 2 capture

引用

Energy Procedia 2011年 4卷 356-361页

作者： Shiying Lin Takashi Kiga Yin Wang Katsuhiro Nakayama Research & Development Department Japan Coal Energy Center Institute of Process Engineering Chinese Academy of Sciences National Institute of Advanced Industrial Science and Technology Japan

One method for reducing CO 2 , the green house gas emissions is to capture CO 2 before it releases into the atmosphere and then sequestrate it. Active lime (main component, CaO) can be used to capture CO 2 in the exhaust gas or in the reactor from fossil fuels utilization effectively. That is calcium oxide (CaO) absorbs CO 2 to yield calcium carbonate (CaCO 3 ) (Eq.(1)), then the CaCO 3 is thermally decomposed to CaO again and release nearly pure CO 2 (Eq. (2)) for sequestration. To obtain a nearly pure CO 2 stream from CaCO 3 decomposition, the heat for decomposing CaCO 3 can be supplied by combusting fossil fuels, such as coal and natural gas, in a calciner with oxygen fuel combustion. The oxygen diluted by CO 2 (CO 2 cycle) or H 2 O (steam cycle), in order to obtain near pure CO 2 stream from CaCO 3 decomposition. In our previous studie s 4-6 , it was clarified that calcinations of limestone (main component, CaCO 3 ) in a fluidized bed calciner can be performed in CO 2 cycle atmosphere when the bed temperature was raised above 1293 K, whereas with 60% steam cycle in atmosphere, limestone can be decomposed at comparatively lower temperature, such as 1173 K. The decomposition conversions of the limestone were about 95% and 98%, in CO 2 cycle and in steam cycle atmospheres, respectively. Reducing the calcinations temperature of limestone was helpful to produce more than 30% active CaO as shown in previous stud y 4-6 . In this study, the energy of CaCO 3 calcination process by H 2 O (steam) cycle was analyzed and compared with CaCO 3 calcination process by CO 2 cycle. For process calculations, the mass and energy flows were calculated iteratively, based on the input and output balances, until err [(input–output)/input] was <0.01. Analysis showed that, although H 2 O (steam) cycle calcination had calcination energy more about 3.6% than CO 2 cycle due to water evaporation latent heat loss, however, the calcination energy per active CaO was lowest for H 2 O (steam) cycl

关键词： CO 2 sorbent Limestone calcinations Reactivity Energy Chemical loop

来源：评论

学校读者我要写书评

暂无评论

Quantitative Analysis of the Removal Ratio of Fine Particles in Water by Gas Bubbling

Quantitative Analysis of the Removal Ratio of Fine Particles...

引用

The 2nd International Symposium on Clean Steel(ISCS 2011)

作者： Masafumi Miyazaki Hideaki Yamamura Satoru Mineta Takehiko Toh Environment & Process Technology Center Technical Development BureauNippon Steel Corp. Advanced Technology Research Lab. Technical Development BureauNippon Steel Corp.

Removal of non-metallic inclusions in molten steel is important from the viewpoint of improvement of quality,property and yield of the *** a removal method of inclusions from molten metal,gas bubble flotation adhering inclusions is well *** bubbling is particularly effective for the removal of fine *** model experiment is reported the quantitative analysis of the removal ratio of dispersed particles removed from water by gas bubbles.

关键词： inclusion gas bubble water model experiment removal constant collision attachment

来源：评论

学校读者我要写书评

暂无评论

Comprehensive understanding of random telegraph noise with

Comprehensive understanding of random telegraph noise with

引用

Symposium on VLSI technology

作者： Y. Higashi N. Momo H. S. Momose T. Ohguro K. Matsuzawa Advanced LSI Technology Laboratory Corporate Research and Development Center Toshiba Corporation Yokohama Japan Device & Process Development Center Corporate Research and Development Center Toshiba Corporation Yokohama Japan

Physical modeling of transient and frequency domain noise simulation for random telegraph noise (RTN) is conducted, considering discretized traps and energy transition in insulator. The models are implemented in a 3D device simulator to consider the device structure effect and bias effect universally. Trap density and trap distribution in insulator are predicted quantitatively with comparison of measured data and simulated data. In addition, we present negative pre-pulse effect for RTN reduction.

关键词： MOS devices Electron traps Mathematical model Noise Current measurement Insulators Frequency domain analysis

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：