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International Symposium on VLSI technology, Systems and Applications

作者： Yoshifumi Nishi Takeshi Sonehara Akira Hokazono Shigeru Kawanaka Satoshi Inaba Atsuhiro Kinoshita Advanced LSI Technology Laboratory Corporate R&D Center Toshiba Corporation Japan Center for Semiconductor Research and Development Toshiba Corporation Semiconductor Company Japan Device and Process Development Center Corporate R&D Center Toshiba Corporation Yokohama Japan

Incorporation of platinum (Pt) into nickel silicide (NiSi) improves the reliability and thermal stability of electrodes in Si MOSFETs. Increasing the Pt content is desirable for further scaled CMOS, but incorporation of more Pt would tremendously increase the material cost. In addition, since Pt is one of the key materials for eco-technology such as catalyst for exhaust absorption and so on, reduction of the use of Pt whose amount is limited is essential for ecology. Recently palladium (Pd), which has similar chemical properties to those of Pt, has been attracting interest as a substitute of Pt. Several works have pointed out that NiPdSi bulk film has superior thermal stability to NiSi. However, its potentiality in fully integrated CMOS devices has not been studied yet. In this work, we investigate the detailed properties of NiPdSi on fully integrated CMOS structures fabricated with the advanced process technology as a candidate of the alternative silicide material for NiPtSi.

关键词： CMOS technology Palladium Nickel Silicides Costs Thermal stability Platinum Electrodes MOSFETs Absorption

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Robust spin-on glass gap-fill process technology for sub-30nm interlayer dielectrics

Robust spin-on glass gap-fill process technology for sub-30n...

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IEEE International Conference on Interconnect technology

作者： Kyung-Mun Byun Deok-Young Jung Jun-Won Lee Seungheon Lee Hyongsoo Kim Mun-Jun Kim Eunkee Hong Mansug Gang Seok-Woo Nam Joo-Tae Moon Chilhee Chung Jung-Hoo Lee Hyo-Sug Lee Process Development Team Semiconductor Research and Development Center USA Manufacturing Technology Team Infra Technology Service Center Semiconductor Business Samsung Electronics Company Limited Hwasung Gyeonggi South Korea Material Application Group Materials Research Center Samsung Advanced Institute of Technology Samsung Electronics Company Limited Yongin si Gyeonggi South Korea

ISBN: (纸本)9781424476763;9781424476770

A highly robust gap-fill process technology of spin-on glass (SOG) was developed for the interlayer dielectric (ILD) in sub-30 nm devices. We revealed that the filling behavior of SOG within gaps during spin-coating is mainly dependent on the capillary effect. The highly wettable surface treatment prior to SOG coating was found to enhance the gap-fill performance remarkably. This technique plays a key role in maximizing capillary effect by raising surface wettability. The filling capability was also improved by optimization of baking temperature to minimize the viscosity of SOG. It was finally found that the defects of contact bridges due to poor filling of SOG were reduced to be almost free by those unique process refinements.

关键词： Robustness Glass Filling Bridges Coatings Dielectric devices Dielectric materials Semiconductor materials Surface treatment Plasma temperature

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Robust spin-on glass gap-fill process technology for sub-30nm interlayer dielectrics

Robust spin-on glass gap-fill process technology for sub-30n...

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2010 IEEE International Interconnect technology Conference, IITC 2010

作者： Byun, Kyung-Mun Jung, Deok-Young Lee, Jun-Won Lee, Seungheon Kim, Hyongsoo Kim, Mun-Jun Hong, Eunkee Gang, Mansug Nam, Seok-Woo Moon, Joo-Tae Chung, Chilhee Lee, Jung-Hoo Lee, Hyo-Sug Process Development Team Semiconductor R and D Center Samsung Electronics Co. Ltd. Hwasung-City Gyeonggi-Do 445-701 Korea Republic of Manufacturing Technology Team Infra Technology Service Center Samsung Electronics Co. Ltd. San#16 Banwol-Dong Hwasung-City Gyeonggi-Do 445-701 Korea Republic of Material Application Group Materials Research Center Samsung Advanced Institute of Technology San#14 Nongseo-Dong Giheung-Gu Yongin-City Gyeonggi-Do 449-712 Korea Republic of

ISBN: (纸本)9781424476763

A highly robust gap-fill process technology of spin-on glass (SOG) was developed for the interlayer dielectric (ILD) in sub-30nm devices. We revealed that the filling behavior of SOG within gaps during spin-coating is mainly dependent on the capillary effect. The highly wettable surface treatment prior to SOG coating was found to enhance the gap-fill performance remarkably. This technique plays a key role in maximizing capillary effect by raising surface wettability. The filling capability was also improved by optimization of baking temperature to minimize the viscosity of SOG. It was finally found that the defects of contact bridges due to poor filling of SOG were reduced to be almost free by those unique process refinements. ©2010 IEEE.

关键词： Coatings

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A NEW NON-INVASIVE METHOD FOR VALVE STICTION DECTION USING WAVELET technology

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Journal of Electronics(China) 2009年第5期26卷 673-680页

作者： Xu Zhanyang Charles Zhan Zhang Shunyi Institute of Information Network Technology Nanjing University of Posts ＆ Telecommunications Nanjing 210003 China Department of Computer Sciences~ Nanjing University of Information Science and Technology Nanjing 210044 China Advanced Process Control Research and Development Group Honeywell Process Solutions Phoenix AZ 85027 USA

In this letter, we present a novel approach of valve stiction detection using wavelet technology. A new non-invasive method is developed with the closed-loop normal operating data. The redundant dyadic discrete wavelet transform is used to decompose the data at different resolution scales. Based on the Lipschitz regularity theory, wavelet coefficients analysis across scales is performed to detect the jumps in the controlled variables. Adaptive wavelet de-noising is then applied to the data. Features of the valve stiction patterns are extracted from the de-noised data and the valve stiction probability is calculated.

关键词： Valve stiction Wavelet de-noising Jump Features extraction

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20nm-node planer MONOS cell technology for multi-level NAND flash memory

20nm-node planer MONOS cell technology for multi-level NAND ...

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2009 Symposium on VLSI technology, VLSIT 2009

作者： Yaegashi, T. Okamura, T. Sakamoto, W. Matsunaga, Y. Toba, T. Sakuma, K. Gomikawa, K. Komiya, K. Nagashima, H. Akahori, H. Sekine, K. Kai, T. Ozawa, Y. Sugi, M. Watanabe, S. Narita, K. Umemura, M. Kutsukake, H. Sakuma, M. Maekawa, H. Ishibashi, Y. Sugimae, K. Koyama, H. Izumida, T. Kondo, M. Aoki, N. Watanabe, T. Center for Semiconductor Research and Development Semiconductor Company Toshiba Corporation 8 Shinsugita-cho Isogo-ku Yokohama 235-8522 Japan Advanced LSI Technology Laboratory Toshiba Corporation Japan Process and Manufacturing Engineering Center Semiconductor Company Toshiba Corporation Japan Advanced Memory Development Center Semiconductor Company Toshiba Corporation Japan

ISBN: (纸本)9784863480094

20nm-node planer MONOS NAND Flash memory is developed for the first time. Excellent performances such as fast program speed are realized without using FinFET structure. Furthermore, potential of tight Vth distribution is confirmed using 50nm-node cells. These properties indicate that planer MONOS cell technology developed in this work can be one of candidates for multi-level NAND Flash memory with 20nm-node and beyond.

关键词： NAND circuits

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development of selective Co CVD capping process for reliability improvement of advanced Cu interconnect

Development of selective Co CVD capping process for reliabil...

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advanced Metallization Conference 2008, AMC 2008

作者： Nakazawa, Emiko Arita, Koji Tsuchiya, Yasuaki Kakuhara, Yumi Yokogawa, Shinji Kurokawa, Tetsuya Sasaki, Nobuyuki Ganguli, Seshadri Ha, Hyoung-Chan Wei, Ti Lee Yu, Sang-Ho Sekine, Makoto Process Technology Division NEC Electronics Corporation 1120 Shimokuzawa Sagamihara Kanagawa 229-1198 Japan Advanced Device Development Division NEC Electronics Corporation 1120 Shimokuzawa Sagamihara Kanagawa 229-1198 Japan Test and Analysis Engineering Division NEC Electronics Corporation 1120 Shimokuzawa Sagamihara Kanagawa 229-1198 Japan Applied Materials Japan 3-20-20 kaigan minato-ku Tokyo 108-8444 Japan Applied Materials 3050 Bowers Ave. Santa Clara CA 95054 United States

ISBN: (纸本)9781605111254

This paper describes Selective Co CVD capping process for advanced Cu/Low-k interconnection with higher reliability. More than 100 times longer EM lifetime with no resistivity increase has been obtained by using this technology. Excellent selectivity has been confirmed from line to line leakage and TDDB lifetime measurements. The Selective Co CVD capping process is the candidate for 32nm node generation and beyond. © 2009 Materials Research Society.

关键词： Integrated circuit interconnects

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Vertical cell array using TCAT(terabit cell array transistor) technology for ultra high density NAND flash memory

Vertical cell array using TCAT(terabit cell array transistor...

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2009 Symposium on VLSI technology, VLSIT 2009

作者： Jang, Jaehoon Kim, Han-Soo Cho, Wonseok Cho, Hoosung Kim, Jinho Sun, Il Shim Jang, Younggoan Jeong, Jae-Hun Son, Byoung-Keun Dong, Woo Kim Kim, Kihyun Shim, Jae-Joo Jin, Soo Lim Kim, Kyoung-Hoon Su, Youn Yi Lim, Ju-Young Chung, Dewill Moon, Hui-Chang Hwang, Sungmin Lee, Jong-Wook Son, Yong-Hoon Chung, U.-In Lee, Won-Seong Advanced Technology Development Team 2 Memory R and D Center Memory Division Yongin-City Gyeonggi-Do 449-711 Korea Republic of Process Development Team Memory R and D Center Memory Division San #24 Nongseo-Dong Giheung-Gu Yongin-City Gyeonggi-Do 449-711 Korea Republic of

ISBN: (纸本)9784863480094

Vertical NAND flash memory cell array by TCAT (Terabit Cell Array Transistor) technology is proposed. Damascened metal gate SONOS type cell in the vertical NAND flash string is realized by a unique 'gate replacement' process. Also, conventional bulk erase operation of the cell is successfully demonstrated. All advantages of TCAT flash is achieved without any sacrifice of bit cost scalability.

关键词： Cells

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Liquid phase oxidation of p-cresol over cobalt saponite

Liquid phase oxidation of p-cresol over cobalt saponite

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作者： Kshirsagar, Vikas S. Garade, Ajit C. Patil, Kashinath R. Shirai, Masayuki Rode, Chandrashekhar V. Chemical Engineering and Process Development Division National Chemical Laboratory Dr. Homi Bhabha Road Pune 411008 India Centre for Materials Characterization Division National Chemical Laboratory Dr. Homi Bhabha Road Pune 411008 India Research Center for Compact Chemical Process National Institute of Advanced Industrial Science and Technology 4-2-1 Nigatake Miyagino Sendai 983-8551 Japan

Liquid phase oxidation of p-cresol was carried out over a Co-saponite catalyst in a temperature and pressure range of 333-393 K and 20-827 kPa, respectively in n-propanol. Co-saponites with varying cobalt content (5-30%) were prepared and screened among which 13% Co-saponite gave the highest conversion of 92% of p-cresol with 92% selectivity to p-hydroxybenzaldehyde without formation of any non-oxidation products. © Springer Science+Business Media, LLC 2009.

关键词： Cobalt

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20nm-node planer MONOS cell technology for multi-level NAND Flash Memory

20nm-node planer MONOS cell technology for multi-level NAND ...

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Symposium on VLSI technology

作者： T. Yaegashi T. Okamura W. Sakamoto Y. Matsunaga T. Toba K. Sakuma K. Gomikawa K. Komiya H. Nagashima H. Akahori K. Sekine T. Kai Y. Ozawa M. Sugi S. Watanabe K. Narita M. Umemura H. Kutsukake M. Sakuma H. Maekawa Y. Ishibashi K. Sugimae H. Koyama T. Izumida M. Kondo N. Aoki T. Watanabe Center of Semiconductor Research & Development Semiconductor Company Toshiba Corporation Yokohama Japan Advanced LSI Technology Laboratory Toshiba Corporation Japan Process & Manufacturing Engineering Center Semiconductor Company Toshiba Corporation Japan Advanced Memory Development Center Semiconductor Company Toshiba Corporation Japan

20 nm-node planer MONOS NAND Flash memory is developed for the first time. Excellent performances such as fast program speed are realized without using FinFET structure. Furthermore, potential of tight Vth distribution is confirmed using 50 nm-node cells. These properties indicate that planer MONOS cell technology developed in this work can be one of candidates for multi-level NAND Flash memory with 20 nm-node and beyond.

关键词： Metalworking machines MONOS devices Dielectric films Voltage FinFETs Electrodes Large scale integration Laboratories Manufacturing processes Semiconductor device manufacture

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Optimization of metallization processes for 32-nm-node highly reliable ultralow-k (k=2.4)/Cu multilevel interconnects incorporating a bilayer low-k barrier cap (k=3.9)

Optimization of metallization processes for 32-nm-node highl...

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International Electron Devices Meeting (IEDM)

作者： M. Iguchi S. Yokogawa H. Aizawa Y. Kakuhara H. Tsuchiya N. Okada K. Imai M. Tohara K. Fujii T. Watanabe Advanced Device Development Division NEC Electronics Corporation Limited Sagamihara Kanagawa Japan Process Technology Division NEC Electronics Corporation Limited Sagamihara Kanagawa Japan Center of Semiconductor Research and Development Toshiba Corporation Yokohama Kanagawa Japan

ISBN: (纸本)9781424456390

Reliability of 32-nm-node ultralow-k (k=2.4)/Cu multilevel interconnects incorporating a bilayer low-k barrier cap (k=3.9) was improved without excessive wiring resistance by using CuAl seed technology with high-temperature and short-time annealing. Though the increase in wiring resistivity was about 10%, both electromigration (EM) and stress-induced voiding (SiV) reliability was clearly improved by using Cu-0.5 wt%Al seed metal.

关键词： Metallization Copper Wiring Annealing Integrated circuit interconnections Semiconductor device reliability Conductivity Grain size Electrical resistance measurement National electric code

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