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Bipolar/BiCMOS Circuits and technology Meeting

作者： Tianbing Chen Jeff Babcock Yen Nguyen Wendy Greig Natasha Lavrovskaya Todd Thibeault Scott Ruby Steve Adler Tracey Krakowski Jonggook Kim Alexei Sadovnikov Advanced Process Technology Development National Semiconductor Corporation Santa Clara CA USA

ISBN: (纸本)9781424427253

Footprint design in SiGe BiCMOS SOI technology is described in this paper to improve device performance matrix. The safe operating area (SOA) for a SiGe hetero-junction bipolar transistor (HBT) fabricated on silicon on insulator (SOI) is significantly improved as the footprint area increases. The Early voltage for SiGe HBT on SOI at medium-high bias range also increases substantially with footprint area increase. Peak f T and noise figure improves slightly with footprint, and peak f MAX improves slightly then decreases significantly at very large footprint area. A generic tube-area-limited thermal resistance model for BiCMOS devices on SOI is also proposed.

关键词： Silicon germanium Heterojunction bipolar transistors Electron tubes Extraterrestrial measurements Electrical resistance measurement Thermal resistance Transistors

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Vertical structure NAND flash array integration with paired FinFET multi-bit scheme for high-density NAND flash memory application

Vertical structure NAND flash array integration with paired ...

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2008 Symposium on VLSI technology Digest of Technical Papers, VLSIT

作者： Koo, June-Mo Yoon, Tae-Eung Lee, Taehee Byun, Sungjae Jin, Young-Gu Kim, Wonjoo Kim, Sukpil Park, Jongbong Cho, Junseok Choe, Jeong-Dong Lee, Choong-Ho Jong, Jin Lee Han, Je-Woo Kang, Yunseung Park, Sangjun Kwon, Byoungho Jung, Yong-Ju Yoo, Inkyoung Park, Yoondong Samsung Advanced Institute of Technology San 14-1 Giheung-Gu Yongin-City Gyeonggi-Do 449-712 Korea Republic of Advanced Technology Development Team 2 Semiconductor R and D Center Samsung Electronics Co. Ltd. Korea Republic of DRAM Process Architecture Team Semiconductor R and D Center Samsung Electronics Co. Ltd. Korea Republic of Process Development Team Semiconductor R and D Center Samsung Electronics Co. Ltd. Korea Republic of FAB Process Technology Development Group 1 Semiconductor R and D Center Samsung Electronics Co. Ltd. Korea Republic of

ISBN: (纸本)9781424418053

Multi-bit Vertical Structure NAND (VsNAND) Flash memories with 32-paired FinFET cell string have been successfully integrated for the first time. Its array integration issues regarding the sub-10nm vertical structure fin could be solved by proper choices of isolation material, ion implantation, and word line patterning. VsNAND Flash array cells with TANOS (TaN/Al2O 3/SiN/SiOx/Si) charge trap structure show possibilities of acceptable program/erase properties and cell Vth distribution characteristics for multi-level NAND Flash application. © 2008 IEEE.

关键词： FinFET

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Etch defect characterization and reduction in hard-mask-based Al interconnect etching

International Journal of Plasma Science and Engineering

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International Journal of Plasma Science and Engineering 2008年第1期2008卷

作者： Lee, Hong-Ji Hung, Che-Lun Leng, Chia-Hao Lian, Nan-Tzu Young, Ling-Wu Yang, Tahone Chen, Kuang-Chao Lu, Chih-Yuan Advanced Module Process Development Division Technology Development Center Macronix International Company Ltd. Li-Hsin Road Hsinchu 300 Taiwan

This paper identifies the defect adders, for example, post hard-mask etch residue, post metal etch residue, and blocked etch metal island and investigates the removal characteristics of these defects within the oxide-masked Al etching process sequence. Post hard-mask etch residue containing C atom is related to the hardening of photoresist after the conventional post-RIE ashing at 275C. An in situ O2 -based plasma ashing on RIE etcher was developed to prevent the photoresist hardening from the high-ashing temperature;followed wet stripping could successfully eliminate such hardened polymeric residue. Post metal etch residue was caused from the attack of the Al sidewall by Cl atoms, and too much CHF3 addition in the Al main etch step passivated the surface of Al resulting in poor capability to remove the Al-containing residue. The lower addition of CHF3 in the Al main etch step would benefit from the residue removal. One possibility of blocked etch metal island creating was due to the micromasking formed on the opening of TiN during the hard-mask patterning. We report that an additional TiN surface pretreatment with the Ar/CHF3 /N2 plasmas could reduce the impact of the micromasking residues on blocked metal etch.

关键词： Photoresists

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Prediction of early failure due to non-visual defect on time-dependent dielectric breakdown of low-k dielectrics: Experimental verification of a yield-reliability model

Prediction of early failure due to non-visual defect on time...

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Annual International Symposium on Reliability Physics

作者： S. Yokogawa D. Oshida H. Tsuchiya T. Taiji T. Morita Y. Tsuchiya T. Takewaki Advanced Device Development Division Japan Process Technology Division NEC Electronics Corporation Limited Sagamihara Kanagawa Japan

A novel method for the prediction of early failure (EF) due to a non-visual defect is proposed for the time-dependent dielectric breakdown (TDDB) of low-k dielectrics. The yield-reliability relation model is modified to evaluate the EFs. The effectiveness of the novel method is experimentally confirmed by using a 65 nm technology node. A bimodal lifetime distribution is used to evaluate the lifetime distribution. The probability of EF can be estimated based on the basis of the results and the defect density of each wafer.

关键词： Dielectric breakdown Predictive models Copper Dielectric materials Large scale integration Dielectric devices Integrated circuit interconnections Qualifications Leakage current National electric code

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Embedded Silicon Germanium (eSiGe) technologies for 45nm nodes and beyond

Embedded Silicon Germanium (eSiGe) technologies for 45nm nod...

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2008 International Workshop on Junction technology(第六届结技术国际研讨会)

作者： Naoyoshi Tamura Yosuke Shimamune Hirotaka Maekawa Advanced Process Development Department Silicon Technology Development Laboratories Fujitsu Laboratories LTD.Fuchigami 50 Akiurno Tokyo 197-0833 Japan

ISBN: (纸本)9781424417377

This paper reviews main technologies of embedded Silicon Germanium (eSiGe) for 45nm node and beyond .There are three key techniques and an item to be considered carefully as follows. The first technique is a low temperature of epitaxial growth at 550℃ to suppress stacking faults in eSiGe layer. The second one is a controlling of recess shape for eSiGe. Sigma(Σ)-shaped recess is applied, because the strain force on the channel of MOSFET is increased effectively by narrowing spacing between source and drain. The third one is to apply particular surface pre-cleaning treatment before the epitaxial growth, to get the excellent SiGe crystallinity. The final item to be considered carefully is Boron concentration in eSiGe, bacause excessive Boron compensates the strain in eSiGe as well as carbon. Finally We demonstrated the /on= 0.795mA/μm@/off=100nA/μm using above key techniques and an item.

关键词： Silicon germanium epitaxy stacking faults embedding metal-oxide-semiconductor field effect transistors Boron narrow space Ganglia

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Intrinsic correlation between mobility reduction and Vt shift due to interface dipole modulation in HfSiON/SiO2 stack by La or Al addition

Intrinsic correlation between mobility reduction and Vt shif...

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International Electron Devices Meeting (IEDM)

作者： Kosuke Tatsumura Takamitsu Ishihara Seiji Inumiya Kazuaki Nakajima Akio Kaneko Masakazu Goto Shigeru Kawanaka Atsuhiro Kinoshita Corporate Research and Development Center Advanced LSI Technology Laboratory Yokohama Japan Advanced LSI Technology Laboratory Corporate Research and Development Center. Toshiba Corporation Yokohama Japan Process & Manufacturing Center Semiconductor Company Yokohama Japan Center For Semiconductor Research & Development Semiconductor Company. Toshiba Corporation Yokohama Japan

Intrinsic correlation between mobility reduction by remote Coulomb scattering (RCS) and threshold voltage shift (DeltaV t ), both of which are induced by interface dipole modulation at high-k/SiO 2 interface, is investigated. Three types of dipole modulation are examined; Al addition, La addition, and changing quality of interfacial SiO 2 layer. Extrinsic scattering components due to increases of interface state and surface roughness are extracted and separated. It is found that RCS due to interface dipole modulation by Al addition increases with increasing DeltaV t , while that by La addition is constant, independent of DeltaV t . Inevitability of additional scattering for DeltaV t is discussed based on two different models for dipole formation mechanisms.

关键词： Scattering High K dielectric materials High-K gate dielectrics Interface states Rough surfaces Surface roughness Threshold voltage MOSFET circuits Large scale integration Laboratories

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A binder-free electrically conductive Ag adhesive using a chemically adsorbed monolayer

A binder-free electrically conductive Ag adhesive using a ch...

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2008 MRS Fall Meeting

作者： Onishi, Shogo Ohkubo, Yuji Soejima, Kazuhiro Ogawa, Kazufumi Department of Advanced Materials Science Graduate School of Engineering Kagawa University 2217-20 Hayashi-cho Takamatsu Kagawa 761-0396 Japan Business Development HQ Process Technology Dvlpmt. Center ALPS Electric Co. Ltd. 3-31 Akedori Izumi-ku Sendai Miyagi 981-3280 Japan

ISBN: (纸本)9781615677603

A binder-free electrically conductive Ag adhesive (Ag-ECA) using a reactive chemically absorbed monolayer (CAM) is developed. The epoxy-terminated CAM was prepared on the surface of the Ag particles by dispersing in the adsorption solution containing 2-(3,4-epoxy-cycrohexyl)-ethyltrimethoxysilane (ECHxES). After washing the Ag particles for removing the excess absorbents, 2-methyl-imidazole as a cross-linker was reacted to the epoxy-terminated CAM at the surface of the Ag particles dispersed in methanol. For increasing the electrical conductivity, Ag-ECA was prepared with the mixture of large (D=1.0 μm) and small (D=0.5 μm) Ag particles. When the mixture ratio (large: small) was 7: 3, the best electrical conductivity of 4.0×104 (Ω·cm)-1 was obtained. Moreover, in order to prepare the more rigid Ag-ECA wires, a copper-imidazole complex was added to the mixture of the Ag particles covered with the reactive CAMs as the cross-linker instead of 2-methyl-imidazole. As the results, the best pencil hardness obtained on the Ag-ECA wire was F, and the best electric conductivity was 2.5×10 5 (Ω·cm)-1. Both of the electric conductivity and the pencil hardness were better than those with the commercially available Ag-ECAs. © 2009 Materials Research Society.

关键词： Monolayers

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Contact resistance reduction of Pt-incorporated NiSi for continuous CMOS scaling ∼ Atomic level analysis of Pt/B/As distribution within silicide films ∼

Contact resistance reduction of Pt-incorporated NiSi for con...

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International Electron Devices Meeting (IEDM)

作者： Takeshi Sonehara Akira Hokazono Haruko Akutsu Tomokazu Sasaki Hiroshi Uchida Mitsuhiro Tomita Hideji Tsujii Shigeru Kawanaka Satoshi Inaba Yoshiaki Toyoshima Center for Semiconductor Research & Development Toshiba Corporation Semiconductor Company Yokohama Kanagawa Japan Process & Manufacturing Engineering Center Toshiba Corporation Semiconductor Company Yokohama Kanagawa Japan Physical Analysis Technology Center Toshiba Nanoanalysis Corporation Yokohama Kanagawa Japan Advanced LSI Technology Laboratory Corporate Research & Development Center Toshiba Corporation Yokohama Kanagawa Japan

Platinum (Pt)-incorporation into nickel silicide films is the promising approach to reduce the contact resistance (R C ) at silicide/Si interface. Physical properties of Ni 1-x Pt x Si films were investigated by using local electrode atom probe (LEAP); The distributions of Pt and dopants (such as As and B) were analyzed both at silicide/Si interface and at silicide grain boundary. The silicide grain-size miniaturization was clearly observed by Pt-incorporation. The impacts of silicide grain size on electrical properties and thermal stability were clarified depending on the Pt concentration. Finally, R C reduction depending on the incorporated-Pt concentration was experimentally shown in both nMOSFETs and pMOSFETs.

关键词： Contact resistance Silicides Nickel Semiconductor films MOSFETs Platinum Electrodes Probes Grain boundaries Grain size

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Investigation of body bias dependence of gate-induced drain leakage current for body-tied fin field effect transistor

Investigation of body bias dependence of gate-induced drain ...

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作者： Yoshida, Makoto Lee, Chul Jung, Kyoung-Ho Kim, Chang-Kyu Kim, Hui-Jung Park, Heungsik Lee, Won-Sok Kim, Keunnam Kahng, Jae-Rok Yang, Wouns Park, Donggun Advanced Technology Development Team 1 Semiconductor R and D Center Samsung Electronics Co. San 016 Banwol-dong Hwasung Gyeonggi-do 445-701 Korea Republic of Process Development Team Semiconductor R and D Center Samsung Electronics Co. San #16 Banwol-dong Hwasung Gyeonggi-do 445-701 Korea Republic of CAE Team Semiconductor R and D Center Samsung Electronics Co. San #16 Banwol-dong Hwasung Gyeonggi-do 445-701 Korea Republic of

The body bias dependence of gate-induced drain leakage (GIDL) current for a fin field effect transistor fabricated on a bulk Si wafer (bulk FinFET) is investigated. The local damascene (LD) bulk FinFET is measured under various bias conditions and the effect of the body-bias-induced lateral electric field on GIDL current is evaluated. A lateral electric field shield effect under fin depleted condition is proposed and it is validated by the three-terminal band-to-band tunneling current model. The GIDL current of the bulk FinFET can be reduced by reducing the body bias, and an improvement in retention characteristics is expected. © 2008 The Japan Society of Applied Physics.

关键词： Fins (heat exchange)

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Impact of tantalum composition in TaC/HfSiON gate stack on device performance of aggressively scaled CMOS devices with SMT and strained CESL

Impact of tantalum composition in TaC/HfSiON gate stack on d...

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Symposium on VLSI technology

作者： M. Goto K. Tatsumura S. Kawanaka K. Nakajima R. Ichihara Y. Yoshimizu H. Onoda K. Nagatomo T. Sasaki T. Fukushima A. Nomachi S. Inumiya H. Oguma K. Miyashita H. Harakawa S. Inaba T. Ishida A. Azuma T. Aoyama M. Koyama K. Eguchi Y. Toyoshima Center for Semiconductor Research and Development Toshiba Corporation Yokohama Kanagawa Japan Advanced LSI Technology Laboratory Corporate Research & Development Center Toshiba Corporation Yokohama Kanagawa Japan Process and Manufacturing Engineering Center Toshiba Corporation Yokohama Kanagawa Japan System LSI Division Semiconductor Company Toshiba Corporation Yokohama Kanagawa Japan

ISBN: (纸本)9781424418022

We report TaC x /HfSiON gate stack CMOS device with simplified gate 1 st process from the viewpoints of fixed charge generation and its impact on the device performance. Moderate Metal Gate / High-K dielectric (MG/HK) interface reaction is found to be a dominant factor to improve device performance. By optimizing TaC x composition, fixed charge free TaC x /HfSiON device is successfully fabricated. Also, we have demonstrated that the strain effect in deeply scaled devices can be enhanced by eliminating the fixed charges in HfSiON, for the first time. Utilizing Stress Memorization Technique (SMT) and strained Contact Etch Stop Layer (CESL), L g = 35 nm high performance TaC x /HfSiON devices is achieved.

关键词： Logic gates Performance evaluation Silicon Strain Metals Dielectrics Materials

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