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A novel robust TiN/AHO/TiN capacitor and CoSi/sub 2/ cell pad structure for 70nm stand-alone and embedded DRAM technology and beyond

A novel robust TiN/AHO/TiN capacitor and CoSi/sub 2/ cell pa...

引用

International Electron Devices Meeting (IEDM)

作者： J.M. Park Y.S. Hwang D.S. Hwang H.K. Hwang S.H. Lee G.Y. Kim M.Y. Jeong B.J. Park S.E. Kim M.H. Cho D.I. Kim J.-H. Chung I.S. Park C.-Y. Yoo J.H. Lee B.Y. Nam Y.R. Park C.-S. Kim M.-C. Sun J.-H. Ku S. Choi H.S. Kim Y.G. Park Kinam Kim Advanced Technology Development Yongin si South Korea Advanced Technology Development Process Development Semiconductor Research and Development Division Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Process Development Semiconductor R&D Div. Samsung Electronics Co. Kiheung-Eup Yongin-City Kyunggi-Do Korea

For the first time, a novel robust (square-shape cylinder type) TiN/AHO (Al/sub 2/O/sub 3/-HfO/sub 2/)/TiN capacitor with Co-silicide on landing cell pad suitable for both stand-alone and embedded DRAMs are successfully developed with 88nm (pitch 176nm) feature size, which is the smallest feature size ever reported in DRAM technology, using ArF lithography for aiming 70nm stand-alone and embedded DRAM technology. The capacitor with Toxeq of 1.5nm and leakage current of less than 1 fA/cell is achieved. The cell contact resistance is greatly improved by using Co-silicidation on landing cell pad and metal storage node contact plug, which results in high performance.

关键词： Tin Robustness Atherosclerosis Random access memory Contact resistance Plugs MIM capacitors Leakage current Capacitance Robust stability

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Fully integrated 64 Kb MRAM with novel reference cell scheme

Fully integrated 64 Kb MRAM with novel reference cell scheme

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International Electron Devices Meeting (IEDM)

作者： H.S. Jeong G.T. Jeong G.H. Koh I.H. Song W.J. Park T.W. Kim S.J. Jeong Y.N. Hwang S.J. Ahn H.J. Kim J.S. Hong W.C. Jeong S.H. Lee J.H. Park W.Y. Cho J.S. Kim S.H. Song S.O. Park U.I. Jeong K. Kim Advanced Technology Development Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Materials & Device Laboratory Samsung Advanced Institute of Technology Yongin si Gyeonggi South Korea Process Development Team Semiconductor Research and Development Division Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Advanced Technology Development

We have fully integrated a 64 Kb MRAM with 0.24 /spl mu/m-CMOS technology. A new sensing scheme employing a separated half-current source is adopted for the reference bit line to increase the sensing signal. To reduce cell resistance, a Co salicidation process is applied to transistor formation. In key fabrication processes, the roughness of the buffer layer, on which the MTJs are stacked, is reduced by using Ru on the TiN bottom electrode, and magnetic disturbance is avoided by depositing TiN hard masks on the MTJ under low-power and low-temperature conditions. The tunneling barrier micro-bridge due to the attachment of by-products during etching is completely eliminated by adopting a 2-step MTJ etch with an introduced capping oxide layer. Consequently, MR values of >30% are found in more than 90% of chips.

关键词： Magnetic tunneling Voltage CMOS technology CMOS process Tin Magnetic separation Etching Clamps Circuits Research and development

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Fragile porous low-k/copper integration by using electro-chemical polishing

Fragile porous low-k/copper integration by using electro-che...

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Symposium on VLSI technology

作者： S. Takahashi K. Tai H. Ohtorii N. Komai Y. Segawa H. Horikoshi Z. Yasuda H. Yamada M. Ishihara T. Nogami Advanced Process R & D Laboratories LSI Technology Development Sony Corporation Semiconductor Network Company Atsugi Kanagawa Japan

A fragile porous ultra-low-k (k=2.2) silica was successfully integrated at trench level in damascene copper by applying our previously reported [1] electro chemical polishing (ECP) technique for Cu. After removing Cu by ECP, the barrier (WN) was removed by low pressure (LP) CMP (<1 psi). Practical polishing rates were obtained for WN in LP-CMP, because of higher chemical sensitivity of WN compared to Ta(N). Compatibility of CVD barrier to porous low-k, excellent barrier performance in aggressive features and lower via resistance were achieved by a newly developed CVD/PVD stacked WN barrier.

关键词： Copper Chemical vapor deposition Chemical technology Silicon compounds Dielectric materials Atherosclerosis Laboratories Large scale integration Electronic mail Chemical processes

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A novel robust TiN/AHO/TiN capacitor and CoSi2 cell pad structure for 70 nm stand-alone and embedded DRAM technology and beyond

A novel robust TiN/AHO/TiN capacitor and CoSi2 cell pad stru...

引用

2002 IEEE International Devices Meeting (IEDM)

作者： Park, J.M. Hwang, Y.S. Hwang, D.S. Hwang, H.K. Lee, S.H. Kim, G.Y. Jeong, M.Y. Park, B.J. Kim, S.E. Cho, M.H. Kim, D.I. Chung, J.-H. Park, I.S. Yoo, C.-Y. Lee, J.H. Nam, B.Y. Park, Y.R. Kim, C.-S. Sun, M.-C. Ku, J.-H. Choi, S. Kim, H.S. Park, Y.G. Kim, Kinam Advanced Technology Development Semiconductor R and D Div. Samsung Electronics Co. San #24 Nongseo-Ri Kiheung-Eup Yongin-City 449-900 Kyunggi-Do Korea Republic of Process Development Semiconductor R and D Div. Samsung Electronics Co. San #24 Nongseo-Ri Kiheung-Eup Yongin-City 449-900 Kyunggi-Do Korea Republic of

For the first time, a novel robust (square-shape cylinder type) TiN/AHO (Al 2O3-HfO2) /TiN capacitor with Co-silicide on landing cell pad suitable for both stand-alone and embedded DRAMs are successfully developed with 88nm (pitch 176nm) feature size, which is the smallest feature size ever reported in DRAM technology, using ArF lithography for aiming 70nm stand-alone and embedded DRAM technology. The capacitor with Toxeq of 1.5nm and leakage current of less than 1fA/cell is achieved. The cell contact resistance is greatly improved by using Co-silicidation on landing cell pad and metal storage node contact plug, which results in high performance.

关键词： Dynamic random access storage

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Fully integrated 64 Kb MRAM with novel reference cell scheme

Fully integrated 64 Kb MRAM with novel reference cell scheme

引用

2002 IEEE International Devices Meeting (IEDM)

作者： Jeong, H.S. Jeong, G.T. Koh, G.H. Song, I.H. Park, W.J. Kim, T.W. Jeong, S.J. Hwang, Y.N. Ahn, S.J. Hong, J.S. Jeong, W.C. Lee, S.H. Park, J.H. Cho, W.Y. Kim, J.S. Song, S.H. Kim, H.J. Park, S.O. Jeong, U.I. Kim, Kinam Advanced Technology Development San #24 Nongseo-Ri Kiheung-Eup Yongin Kyunggi-Do 449-900 Korea Republic of Process Development Team Semiconductor R and D Div. Samsung Electronics Co. Ltd. San #24 Nongseo-Ri Kiheung-Eup Yongin Kyunggi-Do 449-900 Korea Republic of Materials and Device Laboratory Samsung Adv. Institute of Technology San #24 Nongseo-Ri Kiheung-Eup Yongin Kyunggi-Do 449-900 Korea Republic of

We have My integrated a 64 Kb MRAM with 0.24 um-CMOS technology. A new sensing scheme of separated half-current source is adopted for the reference bit line to increase sensing signal. To reduce cell resistance, Co salicidation process is applied to transistor formation. In key fabrication processes, the roughness of buffer layer, on which MTJ is stacked, is reduced by using Ru on TiN bottom electrode, and the magnetic disturbance is avoided by depositing TiN hard mask on MTJ in low-power and low-temperature condition. Especially, the micro-bridge of tunneling barrier due to the attachment of by-products during etching is completely eliminated by adopting 2-step MTJ etch with introducing a capping oxide layer. Consequently, MR values of > 30% are found in more than 90% chips.

关键词： Random access storage

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Improved current performance of CMOSFETs with nitrogen incorporated HfO2-Al2O3 laminate gate dielectric

Improved current performance of CMOSFETs with nitrogen incor...

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International Electron Devices Meeting (IEDM)

作者： Hyung-Seok Jung Yun-Seok Kim Jong Pyo Kim Jung Hyoung Lee Jong-Ho Lee Nae-In Lee Ho-Kyu Kang Kwang-Pyuk Suh Hyuk Ju Ryu Chang-Bong Oh Young-Wug Kim Kyung-Hwan Cho Hion-Suck Baik Young Su Chung Hyo Sik Chang Dae Won Moon Advanced Process Development Project Samsung Electronics Co. Ltd. Yongin-City Kyunggi-Do Korea Technology Development Samsung Electronics Co. Ltd. South Korea Technology Development Samsung Electronics Co. Ltd. Kl Manufacturing Team Samsung Electronics Co. Ltd. Advanced Process Development Project System LSI Business Samsung Electronics Company Limited Yongin si Gyeonggi South Korea AE Center Samsung Advanced Institute of Technology South Korea Nano Surface group Korea Research Institute of Standard and Science South Korea

ISBN: (纸本)0780374622

For the first time, we integrated poly-Si gate CMOSFETs with nitrogen incorporated HfO/sub 2/-Al/sub 2/O/sub 3/ laminate (HfAlON) as gate dielectrics. Both low gate leakage currents (0.1 mA/cm/sup 2/ at V/sub g/=+1.0 V) and low EOT (15.6 /spl Aring/) sufficiently satisfy the specifications (EOT=12/spl sim/20 /spl Aring/, J/sub g/=2.2 mA/cm/sup 2/) estimated by ITRS for low power applications. By in-situ 3 step post-deposition annealing, approximately 17 at.% nitrogen is incorporated at the HfAlON/Si interface. In-situ 3 step post-deposition annealing decreases metallic Hf bonding, which exists at the HfO/sub 2/-Al/sub 2/O/sub 3/ laminate/Si interface. As a result, we can suppress C-V hysteresis and improve current performance. Finally, well-behaved 100 nm CMOSFET devices are achieved. The measured saturation currents at 1.2 V V/sub dd/ are 585 /spl mu//spl Aring///spl mu/m (I/sub off/= 10 nA//spl mu/m) for nMOSFET and 265 /spl mu/A//spl mu/m (I/sub off/=10 nA//spl mu/m) for pMOSFET, which are approximately 80% of those of nitrided SiO/sub 2/. In terms of I/sub on/-I/sub off/ characteristics of n/pMOSFETs, these results represent the best current performance compared with previous reports for poly-Si gate CMOSFETs with high-k gate dielectrics.

关键词： CMOSFETs Nitrogen Hafnium oxide MOSFET circuits Laminates Annealing Dielectrics Leakage current Bonding Capacitance-voltage characteristics

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Device performance of sub-50 nm CMOS with ultra-thin plasma nitrided gate dielectrics

Device performance of sub-50 nm CMOS with ultra-thin plasma ...

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International Electron Devices Meeting (IEDM)

作者： S. Inaba T. Shimizu S. Mori K. Sekine K. Saki H. Suto H. Fukui M. Nagamine M. Fujiwara T. Yamamoto M. Takayanagi I. Mizushima K. Okano S. Matsuda H. Oyamatsu Y. Tsunashima S. Yamada Y. Toyoshima H. Ishiuchi SoC Research & Development Center Toshiba Corporation Semiconductor Company Yokohama Japan SoC Research & Development Center Process & Manufacturing Engineering Center Toshiba Corporation Semiconductor Company Yokohama Japan Advanced LSI Technology Laboratories Corporate Research and Development Toshiba Corporation Yokohama Japan Advanced Logic Technology Department System LSI Division Toshiba Corporation Semiconductor Company Yokohama Japan

In this paper, the physical and electrical characteristics of ultra-thin plasma nitrided gate dielectrics are reported, aiming for sub-50 nm gate length CMOS applications. The impact of plasma nitridation conditions on DC characteristics was investigated extensively by changing nitrogen plasma pressure, plasma immersion time, or plasma generation power. NBTI has been also investigated and the lifetime at 105/spl deg/C and 0.85 V operation is estimated to be about 10 years. The final current drives of 690 /spl mu/A//spl mu/m for nFET and 301 /spl mu/A//spl mu/m for pFET at Vdd = 0.85 V (Ioff = 100 nA//spl mu/m) have been achieved in sub-50 nm CMOS with optimized plasma nitrided gate dielectric with EOT <1.2 nm.

关键词： Plasma devices Dielectric devices Plasma applications Plasma properties Electric variables Nitrogen DC generators Character generation Power generation Niobium compounds

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Implanted-ion dose variation from Si surface status of sub-nm scale on 90 nm ULSI process

Implanted-ion dose variation from Si surface status of sub-n...

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International Conference on Ion Implantation technology Proceedings

作者： M. Kase T. Kubo K. Watanabe K. Okabe H. Nakao Advanced LSI Development Division Fujitsu Limited Akiruno Tokyo Japan Fujitsu VLSI Process Technology Laboratory Limited Akiruno Tokyo Japan C project Fujitsu Laboratories Limited Akiruno Tokyo Japan

To make a shallow junction, understanding the influence of the Si surface status is quite important to achieve stable-dose implanted layers. The causes or dose variation can be a sub-nm screening/capping oxide and silicon loss, which originate from the wet chemical processes, the photo resist processes and the clean room environment. These phenomena are examined using SIMS, sheet resistance and the transistor characteristics of a 90 nm node of high end CMOS logic device.

关键词： Ultra large scale integration Implants Surface resistance Surface treatment Laboratories Chemical processes CMOS technology Fabrication Large scale integration Very large scale integration

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Mass production worthy HfO/sub 2/-Al/sub 2/O/sub 3/ laminate capacitor technology using Hf liquid precursor for sub-100 nm DRAMs

Mass production worthy HfO/sub 2/-Al/sub 2/O/sub 3/ laminate...

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International Electron Devices Meeting (IEDM)

作者： Jung-Hyoung Lee Jong Pyo Kim Jong-Ho Lee Yun-Seok Kim Hyung-Seok Jung Nae-In Lee Ho-Kyu Kang Kwang-Pyuk Suh Mun-Mo Jeong Kyu-Taek Hyun Hion-Suck Baik Young Su Chung Xinye Liu S. Ramanathan T. Seidel J. Winkler A. Londergan Hae young Kim Jung Min Ha Nam Kyu Lee Advanced Process Development Project Samsung Electronics Co. Ltd. Yongin-City Kyunggi-Do Korea DRAM PA Team Samsung Electronics South Korea AE Center Samsung Advanced Institute of Technology Genus Inc. Sunnyvale CA USA

For the first time, we successfully demonstrated MIS capacitor with ALD (Atomic Layer Deposition) grown HfO/sub 2/-Al/sub 2/O/sub 3/ laminate film using Hf liquid precursor (Hf(NEtMe)/sub 4/) with EOT of 22.5 /spl Aring/ and acceptable leakage currents (1.0 fA/cell at 1.65 V) which is comparable to the smallest reported value. Advantages of Hf(NEtMe)/sub 4/ liquid precursor for DRAM capacitor dielectric are excellent step coverage (94% on high aspect ratio(>40:1)) and reasonable throughput (over two times higher than that of HfCl/sub 4/ solid precursor). This study will provide practical solution for chip-making industry in terms of mass production worthy process for sub-100 nm DRAM capacitor.

关键词： Mass production Hafnium oxide Capacitors Atomic layer deposition Laminates Leakage current Random access memory Dielectric liquids Throughput Solids

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Improved current performance of CMOSFETs with nitrogen incorporated HfO2-Al2O3 laminate gate dielectric

Improved current performance of CMOSFETs with nitrogen incor...

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2002 IEEE International Devices Meeting (IEDM)

作者： Jung, Hyung-Seok Kim, Yun-Seok Kim, Jong Pyo Lee, Jung Hyoung Lee, Jong-Ho Lee, Nae-In Kang, Ho-Kyu Suh, Kwang-Pyuk Ryu, Hyuk Ju Oh, Chang-Bong Kim, Young-Wug Cho, Kyung-Hwan Baik, Hion-Suck Chung, Young Su Chang, Hyo Sik Moon, Dae Won Advanced Process Development Project System LSI Business Samsung Electronics Co. Ltd. San 24 Nongseo-Ri Kiheung-Eup Yongin-City Kyunggi-Do 449-711 Korea Republic of AE Center Samsung Advd. Inst. of Technology Gyungyi-Do Korea Republic of Nano Surface group Korea Res. Inst. of Std. and Science Taejon Korea Republic of

For the first time, we integrated poly-Si gate CMOSFETs with nitrogen incorporated HfO2-Al2O3 laminate (HfAlON) as gate dielectrics. Both low gate leakage currents (0.1mA/cm2 at Vg=+1.0V) and low EOT (15.6 Å) sufficiently satisfy the specifications (EOT=12∼20Å, Jg=2.2mA/cm2) estimated by ITRS for low power applications. By in-situ 3 step post-deposition annealing, approximately 17 at.% nitrogen is incorporated at the HfAlON/Si interface. In-situ 3 step post-deposition annealing decreases metallic Hf bonding, which exists at the HfO2-Al2O3 laminate/Si interface. As a result, we can suppress C-V hysteresis and improve current performance. Finally, well-behaved 100 nm CMOSFET devices are achieved. The measured saturation currents at 1.2V Vdd are 585μA/μm (Ioff=10nA/μm) for nMOSFET and 265μA/μm (Ioff=10nA/ μm) for pMOSFET, which are approximately 80% of those of nitrided SiO2. In terms of Ion-Ioff characteristics of n/pMOSFETs, these are the best current performance compared with previous reports for the poly-Si gate CMOSFETs with high-k gate dielectrics.

关键词： MOSFET devices

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